JPH0756543A - LCD drive circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] Even if the number of input bits of the data driver increases, it can be configured without increasing the number of input terminals, and the rearrangement of the liquid crystal display device can be realized with a simple configuration. The purpose is to provide. [Structure] A data driver 3 for inputting image signals Rd, Gd, and Bd having digital values of red R, green G, and blue B and driving data lines 2-1 to 2-p of a liquid crystal display panel 1 is provided. A drive circuit of a liquid crystal display device,
Parallel-serial conversion means 11 that serially converts the video signals Rd, Gd, and Bd given in parallel based on a control clock CLK3 having a frequency three times higher than the video signals Rd, Gd, and Bd, and supplies the data driver 3 with the parallel-serial conversion means. It is configured to have serial-parallel conversion means 13 for returning the serial data Sd supplied from the parallel-serial conversion means 11 to the original parallel data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit for a liquid crystal display device, and more particularly to a data rearrangement system for each color of RGB (red, green, blue) and a data driver having a smaller number of input terminals. The present invention relates to a drive circuit of a liquid crystal display device.

At present, liquid crystal display devices are required to have full-color display as well as high definition and high quality. The drive circuit of a liquid crystal display device is roughly classified into an analog system and a digital system. The analog method enables full-color display by capturing an analog value with a sampling circuit, while the digital method obtains a display close to full-color by increasing the number of bits of input data to the drive circuit. . Therefore, it is necessary to increase the number of bits of the input data in order to obtain a display closer to full color with a digital drive circuit.

[0003]

2. Description of the Related Art FIG. 8 is a block diagram of a drive circuit of a conventional liquid crystal display device. In this conventional example, a latch circuit and a shift register are used to capture digital data. Therefore, when the drive circuit is mounted on a COG (Chip On Glass), the data line must be wired on the glass substrate. Therefore, if the number of bits of the input data is large, the wiring is large, and the wiring is high due to crossover. Problems such as resistance increase and the area expansion of the glass substrate have occurred.

Further, when the arrangement of each color of the liquid crystal display panel is a delta arrangement as shown in FIG. 9, the data line of the first data line in the first scanning line and the second scanning line. Since the color signals of are different, it is necessary to interchange the signals for each line. Therefore, since the output terminal depends on the input data, when it is desired to output different color signals to the output terminal, the data must be exchanged by a selector or the like before inputting to the drive circuit.

[0005]

Therefore, in the drive circuit of the conventional liquid crystal display device, when the number of bits of the input data increases, the number of input terminals which is three times that of the input data is required (for example, 8).
When inputting bit data, 8 × 3 (RGB) = 2
(4 input terminals are required), and when COG mounting is performed, problems such as an increase in the area of the glass substrate occur.

Therefore, it is better that the number of input terminals of the drive circuit is smaller, and also in the rearrangement of the RGB color data, a circuit dedicated for rearrangement is required, which causes a problem that the amount of hardware increases.

The present invention solves the above problems,
An object of the present invention is to provide a drive circuit of a liquid crystal display device which can be configured without increasing the number of input terminals even when the number of input bits of a data driver is large, and can rearrange data of each color with a simple configuration.

[0008]

In order to solve the above-mentioned problems, the drive circuit of the liquid crystal display device of the first feature of the present invention is
As shown in FIG. 1, red (R), green (G), and blue (B) digital value video signals Rd, Gd, and Bd.
Data line 2-1 to 2 of the liquid crystal display panel 1 by inputting
A driving circuit for a liquid crystal display device comprising a data driver 3 for driving -p, wherein the video signals Rd, Gd, and B
The video signals Rd, Gd, and Bd applied in parallel based on a control clock CLK3 having a frequency three times d.
Is configured to have parallel-serial conversion means 11 that serial-converts the data to be supplied to the data driver 3.

The liquid crystal display device drive circuit according to the second aspect of the present invention is the liquid crystal display device drive circuit according to claim 1, wherein the data driver 3 is supplied from the parallel-serial conversion means 11. Serial data Sd
To serial parallel conversion means 13 for returning the original parallel data.

A third aspect of the present invention is a drive circuit for a liquid crystal display device, wherein the parallel-serial conversion means 1 is the drive circuit for a liquid crystal display device according to claim 1 or 2.
1 performs rearrangement of colors when serially converting the video signals Rd, Gd, and Bd of the respective colors.

A fourth aspect of the present invention provides a drive circuit for a liquid crystal display device, wherein the serial-parallel conversion means 13 is the same as the original drive circuit for the liquid crystal display device according to the first, second or third aspect. When performing parallel conversion to a video signal, the colors are rearranged.

Further, as shown in FIG. 6, the drive circuit of the liquid crystal display device of the fifth feature of the present invention has red (R), green (G), and blue (B) m bits (m ≧ 2). ) Digital data image signals Rd, Gd, and Bd are input to drive the data lines 2-1 to 2-p of the liquid crystal display panel 1, or a monochrome or monochromatic m-bit digital value. Is a driving circuit of a liquid crystal display device including a data driver 3 ′ for driving the data lines 2-1 to 2-p of the liquid crystal display panel 1 by inputting the video signal Data of Based on the control clock CLK3 of the frequency of ≧ 2), the video signals Rd, Gd, and Bd of m-bit (m ≧ 2) digital value of each color, or the video signal Data of m-bit digital value of monochrome or monochrome are output. It is converted to m / n-bit data constituting a conversion means 15 to be supplied to the data driver 3 '.

The drive circuit of the liquid crystal display device according to the sixth aspect of the present invention is the drive circuit of the liquid crystal display device according to claim 5, wherein the data driver 3 ′ is supplied from the conversion means 15. It comprises an inverse conversion means 17 for returning the data to the original video signal.

[0014]

In the drive circuit of the liquid crystal display device having the first, second, third and fourth features of the present invention, as shown in FIG. The R data Rd, the G data Gd, and the B data Bd are matched during one data time to generate data Sd, which is supplied to the serial / parallel conversion means 13 in the data driver 3, and then the serial / parallel conversion means 13 is generated. Then, clocks CK1, CK2, and CK3 are generated, S data Sd is set in the flip-flops FF1, FF2, and FF3 at respective rising timings, and R is set in the flip-flop FF1 (X data Xd).
The color video signal is the flip-flop FF2 (Y data Y
In d), the G color video signal is input to the flip-flop FF3.
The video signals of B color are respectively held in (Z data Zd), and the original parallel data is restored.

When the parallel-serial conversion means 11 rearranges the colors, the timing of the first selection signal SEL1 is changed, and further the data driver 3 is used.
When the rearrangement of colors is performed by the serial / parallel conversion means 13 therein, it is performed by changing the timing of the second selection signal SEL2.

Therefore, according to the present invention, the video signal input to the data driver 3 can be reduced from the video signals of three RGB colors to one serial data Sd, and the number of input terminals can be reduced. Further, the parallel-serial conversion means 11 performs timing control by the first selection signal SEL1 and the serial-parallel conversion means 13 performs timing control by the second selection signal SEL2, so that colors can be easily rearranged.

Further, in the drive circuit of the liquid crystal display device having the fifth and sixth characteristics of the present invention, as shown in FIG. 6, each of m bits of red (R), green (G), and blue (B) ( m
Video signals Rd, Gd, and Bd having digital values of ≧ 2)
Data line 2-1 to 2 of the liquid crystal display panel 1 by inputting
-P data driver 3 ', or monochrome or monochrome m-bit digital video signal Dat
Input a and enter the data lines 2-1 to 2-1 of the liquid crystal display panel 1.
A driving circuit of a liquid crystal display device including a data driver 3 ′ for driving 2-p, wherein the conversion means 15 controls the control clock C having a frequency n times (n ≧ 2) times the video signal Data.
Based on LK3, m-bit (m ≧ 2) digital-valued video signals Rd, Gd, and Bd for each color, or monochrome or monochrome m-bit digital-valued video signal Data.
Is converted into m / n bit data and supplied to the data driver 3 ', and the inverse conversion means 1 in the data driver 3'is provided.
7, the data supplied from the conversion means 15 is restored to the original video signal.

Therefore, an arbitrary m-bit video signal can be converted into m / n-bit data by a control clock having a frequency of n times and interfaced with the data driver 3 '. The number of input terminals of the driver 3'can be reduced.

[0019]

Embodiments of the present invention will now be described with reference to the drawings. First Embodiment FIG. 1 shows a block diagram of a drive circuit of a liquid crystal display device according to a first embodiment of the present invention. In FIG. 1, the same parts as those in FIG. 8 (conventional example) are designated by the same reference numerals.

The drive circuit of the liquid crystal display device of this embodiment comprises a liquid crystal display panel 1 to be driven and a video signal R of digital values of red (R), green (G) and blue (B).
Data driver 3 for inputting d, Gd, and Bd to drive the data lines 2-1 to 2-p of the liquid crystal display panel 1.
And a scan driver 5 that drives the scan lines 4-1 to 4-q, and a video signal Rd, Gd, and Gd that are applied in parallel based on a control clock CLK3 having a frequency three times higher than the video signals Rd, Gd, and Bd. Parallel-serial conversion means 11 for converting Bd to serial and supplying it to the data driver 3.
And is configured.

Further, the data driver 3 serially / parallel converter 1 restores the serial data Sd supplied from the parallel / serial converter 11 to the original parallel data.
3, shift register 23, latches Lx, Ly, and L
z and the LCD driver 25.

Further, the serial / parallel conversion means 13 is
Clock generation circuit 21 and flip-flop FF
1, FF2, and FF3. The scan driver 5, the shift register 23 in the data driver 3, the latches Lx, Ly, and Lz, and the LCD driver 25 are the same as the conventional ones, and therefore detailed description thereof will be omitted. Here, parallel-serial conversion is performed. Means 1
1 and the serial-parallel conversion means 13 will be described in detail.

FIG. 2 is a detailed circuit diagram of the parallel-serial conversion means 11. Video signals having digital values of red, green, and blue, that is, R data Rd, G data Gd, and B data Bd are output D0 and D1 of the counter CT1.
Selected as the S data Sd.
That is, the R data Rd is G when the counter CT1 output (D0, D1) in the AND gate A1 is (0, 0).
The data Gd is counter CT in the AND gate A2.
When 1 output (D0, D1) is (1, 0), B data Bd
Outputs the counter CT1 (D
When 0, D1) is (0, 1), it is selected respectively.

In other words, the counter CT1 is set to 0, by the control clock CLK3 having a frequency three times as high as that of the video signal.
By being counted as 1, 2, the video signal R of each color of RGB
In d, Gd, and Bd, three data are inserted in the order of R data Rd, G data Gd, and B data Bd during one clock time. This situation is shown in the timing chart of FIG.

The clear signal terminal C of the counter CT1
The output of the OR gate OR1 is connected to LR, but the output of the counter CT1 is shifted by controlling the timing of the first selection signal SEL1, and the video signals Rd, Gd, and Bd of the respective colors are displayed in the order of RGB. Even if you put
The arrangement of clock time signals is "RGB", "GBR",
It can be changed to "BRG". In other words, the parallel / serial conversion means 11 uses the video signals Rd and G of the respective colors.
When serially converting d and Bd, the first selection signal S
Colors can be rearranged by controlling the timing of EL1.

Next, the serial / parallel conversion means 13 will be described with reference to FIG. FIG. 4A is a circuit diagram of the clock generation circuit 21. The clock CK is the control clock CLK3, and the start pulse SP is the second selection signal SEL.
It is configured by a 2-bit 3-bit shift register.
Further, FIG. 4B shows an output clock CK of the clock circuit 21.
3 is a timing chart showing signal waveforms of 1, CK2, and CK3. These clocks CK1, CK2, and C
At the timing of K3, the flip-flops FF1 and FF
2, and S data is set in FF3.

In the serial / parallel conversion means 13,
As a method of rearranging colors when performing parallel conversion to the original video signal, by changing the timing of the second selection signal SEL2 which is the start pulse of the clock generation circuit 21, the S data Sd input side by side in RGB order is input.
Can be made variable as “RGB”, “GBR”, and “BRG”.

Next, FIG. 5 is a timing chart for explaining the operation of the drive circuit of the liquid crystal display device of this embodiment. As shown in FIG. 5A, first, by the parallel-serial conversion means 11, image signals of RGB colors, that is, R data R
The d, G data Gd, and B data Bd are matched during one data time to generate data Sd, which is supplied to the serial / parallel conversion means 13 in the data driver 3.

Next, in the serial / parallel conversion means 13, the clocks CK1, CK2 and CK2 shown in FIG.
And CK3 are generated, and the S data Sd is set in the flip-flops FF1, FF2, and FF3 at the respective rising timings. Therefore, as shown in FIG. 5C, the flip-flop FF1 (X data Xd) receives the R color video signal, and the flip-flop FF2 (Y data Yd) receives the G color video signal.
3 (Z data Zd) holds the B color video signals, respectively, and returns to the original parallel data.

As described above, in the drive circuit of the liquid crystal display device of this embodiment, the video signal input to the data driver 3 can be reduced from three to one serial data Sd, and the number of input terminals can be reduced. it can. Further, the serial-parallel conversion means 11 performs timing control by the first selection signal SEL1 and the parallel-serial conversion means 13 performs timing control by the second selection signal SEL2, so that colors can be easily rearranged. Second Embodiment FIG. 6 shows a configuration diagram of a drive circuit of a liquid crystal display device according to a second embodiment of the present invention. In this embodiment, the liquid crystal display panel 1 is driven by inputting a 3-bit monochrome or monochromatic video signal Data.

The drive circuit of the liquid crystal display device of this embodiment comprises a liquid crystal display panel 1, a data driver 3'for driving the data lines 2-1 to 2-p, and scanning for driving the scanning lines 4-1 to 4-q. Based on the driver 5 and the control clock CLK3 having a frequency three times (n = 3) the video signal Data,
The supplied 3-bit (m = 3) video signal Data is set to 1
It is composed of a conversion means 15 which converts the data into bits (m / n = 1) and supplies the data to the data driver 3 ′.

The data driver 3'includes the conversion means 1
5, the inverse conversion means 17, the shift register 23, and the latch 24 for returning the serial data Sd supplied from 5 to the original video signal.
(Lx, Ly, and Lz), and LCD driver 25
Further, the inverse conversion means 17 includes a clock generation circuit 21 ′ and flip-flops FF1, FF2.
And FF3.

Also in this embodiment, the conversion means 15 uses the control clock CLK3 having a frequency three times as high as that of the video signal Data to convert 3-bit data into 1-bit data, that is, 3 bits per clock time. The data is converted into the data, and the serial data Sd is supplied to the inverse conversion means 17. The inverse conversion means 17 converts the original video signal by setting the flip-flops FF1, FF2, and FF3 at the clock timing generated by the clock generation circuit 21 '.

Therefore, the video signal input to the data driver 3'can be reduced from 3 bits to 1 bit, and the number of input terminals can be reduced. Further, in this embodiment, m
= 3, n = 1 has been described, but even for an arbitrary m-bit video signal, by using a control clock having a frequency of n times, the data is converted into m / n-bit data. It is possible to interface with the driver 3'and reduce the number of input terminals of the data driver 3 '. Third Embodiment FIG. 7 shows a configuration diagram of a drive circuit of a liquid crystal display device according to a third embodiment of the present invention. This embodiment is a modification of the first or second embodiment.

The data driver 3 "of this embodiment is an LCD
Driver 25, control clock CLK3 to clock CK
Clock generation circuit 2 for generating 1, CK2, and CK3
1 ″, latches Lx, Ly, and Lz corresponding to each color signal or each bit data, and shift register SR1,
It is composed of SR2 and SR3.

The parallel-serial converted serial data Sd is input to the digital driver 3 ". The clock generation circuit 21" converts the control clock CLK3 having the frequency three times the frequency of the original video signal to the clock CK1.
Data of each color or each bit is taken in by generating CK2 and CK3 and shifting the operation of the shift register by one clock of the clock. This allows
The same effects as those of the first and second embodiments are obtained.

[0037]

As described above, according to the present invention,
A (parallel-serial) conversion means converts a video signal into serial data, and a clock generation circuit in the data driver,
The number of input terminals of the data driver can be reduced by inversely converting the original video signal with the conversion means (serial parallel or inverse) including flip-flops.
By performing timing control by the first selection signal in the serial / parallel conversion means and timing by the second selection signal in the parallel / serial conversion means, the colors can be easily rearranged, and as a result, the number of input bits of the data driver is large. Even so, it is possible to provide a drive circuit of a liquid crystal display device that can be configured without increasing the number of input terminals and that can rearrange data of each color with a simple configuration.

The drive circuit of the liquid crystal display device of the present invention is
It has an effect of reducing the wiring on the glass substrate when the data driver is mounted by COG, and largely contributes to the performance improvement of the liquid crystal display device.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a drive circuit of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a detailed circuit diagram of parallel-serial conversion means.

FIG. 3 is a timing chart of parallel-serial conversion means.

FIG. 4 is an explanatory diagram of a clock generation circuit, and FIG.
Is a circuit diagram, and FIG. 4B is an output clock C of the clock circuit.
It is a timing chart which shows the signal waveform of K1, CK2, and CK3.

FIG. 5 is a timing chart explaining the operation of the drive circuit of the liquid crystal display device of the first embodiment.

FIG. 6 is a configuration diagram of a drive circuit of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 7 is a configuration diagram of a drive circuit of a liquid crystal display device according to a third embodiment of the present invention.

FIG. 8 is a configuration diagram of a drive circuit of a conventional liquid crystal display device.

FIG. 9 is a configuration diagram of a liquid crystal display panel in which cells of respective colors are arranged in a delta arrangement.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display panel 2-1 to 2-p ... Data line 3, 3 ', 3 ", 103 ... Data driver 4-1 to 4-q ... Scan line 5 ... Scan driver 11 ... Parallel-serial conversion means 13 ... Serial Parallel conversion means 15 ... Conversion means 17 ... Inverse conversion means 21 ... Clock generation circuit (3-bit shift register) 21 ', 21 "... Clock generation circuit SP ... Start pulse FF1, FF2, FF3 ... Flip-flop 23 ... Shift register 24 ... Latch Lx, Ly, Lz ... Latch 25 ... LCD driver Rd ... Red video signal (R data) Gd ... Green video signal (G data) Bd ... Blue video signal (B data) CLK3 ... Control clock Sd ... Serial data (S data) CT1 ... Counter CLR ... Clear signal terminal D0, D1 ... Output of counter CT1 1-A3 ... AND gate OR1, OR2 ... OR gate i1-i4 ... NOT gate SEL1 ... First selection signal SEL2 ... Second selection signal CK1, CK2, CK3 ... Output clock of clock circuit 21 Data ... 3-bit monochrome or monochrome Video signal SR1, SR2, SR3 ... Shift register 105 ... Selector

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masanori Nakamura, 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa, Fujitsu Limited (72) Inventor Naoto Sato, 1015, Kamikodanaka, Nakahara-ku, Kawasaki, Kanagawa Prefecture, Fujitsu Limited

Claims (6)

[Claims] 1. Red (R), green (G), and blue (B) digital value video signals (Rd, Gd, and B)
A driving circuit of a liquid crystal display device comprising a data driver (3) for inputting d) to drive the data lines (2-1 to 2-p) of the liquid crystal display panel (1), the video signal (Rd, Parallel serial based on the control clock (CLK3) having a frequency three times higher than Gd and Bd) and serially converting the video signals (Rd, Gd, and Bd) given in parallel to the data driver (3). A drive circuit for a liquid crystal display device, comprising a conversion means (11). 2. The data driver (3) has serial-parallel conversion means (13) for returning serial data (Sd) supplied from the parallel-serial conversion means (11) to original parallel data. The drive circuit of the liquid crystal display device according to claim 1. 3. The parallel-serial conversion means (11)
3. The drive circuit of the liquid crystal display device according to claim 1, wherein the color rearrangement is performed when the video signals (Rd, Gd, and Bd) of each color are serially converted. 4. The serial-parallel conversion means (13)
The drive circuit of the liquid crystal display device according to claim 2, wherein the color rearrangement is performed when the original video signals are converted into parallel signals. 5. A liquid crystal display panel by inputting video signals (Rd, Gd, and Bd) of digital values of m bits (m ≧ 2) of red (R), green (G), and blue (B), respectively. A data driver (3 ') for driving the data lines (2-1 to 2-p) of (1) or a liquid crystal display panel () by inputting a video signal (Data) of a monochrome or monochromatic m-bit digital value. 1) Data line (2-1 to 2)
-P) is a drive circuit of a liquid crystal display device including a data driver (3 '), wherein each color is based on a control clock (CLK3) having a frequency n times (n≥2) the video signal (Data). m bits (m
Video signals (Rd, Gd, and B) with digital values of ≧ 2)
d) or a conversion means (15) for converting an image signal (Data) of a monochrome or monochromatic m-bit digital value into m / n-bit data and supplying it to the data driver (3 ′). The drive circuit of the liquid crystal display device. 6. The data driver (3 ′) according to claim 5, further comprising an inverse conversion means (17) for returning the data supplied from the conversion means (15) to an original video signal. Drive circuit of the liquid crystal display device.