JPH0810973Y2 - Full wave rectifier circuit - Google Patents
Full wave rectifier circuitInfo
- Publication number
- JPH0810973Y2 JPH0810973Y2 JP1989134160U JP13416089U JPH0810973Y2 JP H0810973 Y2 JPH0810973 Y2 JP H0810973Y2 JP 1989134160 U JP1989134160 U JP 1989134160U JP 13416089 U JP13416089 U JP 13416089U JP H0810973 Y2 JPH0810973 Y2 JP H0810973Y2
- Authority
- JP
- Japan
- Prior art keywords
- current
- voltage
- input
- transistor
- input voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D1/00—Demodulation of amplitude-modulated oscillations
- H03D1/14—Demodulation of amplitude-modulated oscillations by means of non-linear elements having more than two poles
- H03D1/18—Demodulation of amplitude-modulated oscillations by means of non-linear elements having more than two poles of semiconductor devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/4508—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using bipolar transistors as the active amplifying circuit
- H03F3/45085—Long tailed pairs
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Rectifiers (AREA)
- Amplifiers (AREA)
Description
【考案の詳細な説明】 （イ）産業上の利用分野 本考案は、全波整流回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a full-wave rectifier circuit.
（ロ）従来の技術 第２図は、従来の全波整流回路を示す回路図である。(B) Conventional Technique FIG. 2 is a circuit diagram showing a conventional full-wave rectifier circuit.
第２図において、トランジスタQ1,Q2は差動増幅器を
構成しており、トランジスタQ1のベースには基準電圧V
refが印加され、トランジスタQ2のベースには抵抗Ｒを
介した入力電圧VINが印加される。ここで、トランジス
タQ2のベースは、トランジスタQ7,Q8のエミッタ出力が
全帰還されて仮想接地点とされており、更に、入力電圧
VINは、抵抗Ｒによって電流変換されてトランジスタQ2
のベースに印加される。これより、抵抗Ｒを流れる電流
はVIN/Rで表されることになるが、該電流は、仮想接地
点に対する入力電圧の極性に応じて、流れる方向が異な
る。つまり、入力電圧VINが基準電圧Vrefより大の時、
前記電流はトランジスタQ8に供給され、入力電圧VINが
基準電圧Vrefより小の時、前記電流はトランジスタQ7か
ら供給される。従って、入力電圧VINの極性に拘らず、
抵抗RLの両端には正電圧が現れ、該正電圧がコンデンサ
Ｃによって平滑され、全波整流された出力電圧VOUTが得
られる。In FIG. 2, the transistors Q 1 and Q 2 form a differential amplifier, and the base of the transistor Q 1 has a reference voltage V
ref is applied, and the input voltage V IN via the resistor R is applied to the base of the transistor Q 2 . Here, the base of the transistor Q 2 is set to a virtual ground point by fully feeding back the emitter outputs of the transistors Q 7 and Q 8 and further to the input voltage.
V IN is converted into a current by the resistor R and the transistor Q 2
Applied to the base of. From this, the current flowing through the resistor R is represented by V IN / R, but the current flows in different directions depending on the polarity of the input voltage with respect to the virtual ground point. That is, when the input voltage V IN is higher than the reference voltage V ref ,
The current is supplied to the transistor Q 8, the input voltage V IN is when small than the reference voltage V ref, the said current is supplied from the transistor Q 7. Therefore, regardless of the polarity of the input voltage V IN ,
A positive voltage appears across the resistor R L , the positive voltage is smoothed by the capacitor C, and the full-wave rectified output voltage V OUT is obtained.
（ハ）考案が解決しようとする課題 しかしながら、前記従来の技術の場合、入力電圧VIN
が基準電圧Vrefより大となると、トランジスタQ8のエミ
ッタ電流は増大する。そこで、トランジスタQ8のベース
には、最大入力電圧VINに応じたベース電流を定電流源
（１）によって常時供給しなければならない。従って、
消費電流が大となる問題点があった。(C) Problems to be Solved by the Invention However, in the case of the above conventional technique, the input voltage V IN
Becomes larger than the reference voltage V ref , the emitter current of the transistor Q 8 increases. Therefore, the base current corresponding to the maximum input voltage V IN must be constantly supplied to the base of the transistor Q 8 by the constant current source (1). Therefore,
There is a problem that the current consumption becomes large.
更に、電源電圧VCCは、 VCC＝Vref＋Vsat＋２VBE Vsat：トランジスタQ4の飽和電圧 VBE：トランジスタQ5,Q7のベース・エミッタ間電圧 となり、第２図回路を小型機器等に使用した場合、減電
圧特性が悪くなる問題点があった。Further, the power supply voltage V CC becomes V CC = V ref + V sat + 2V BE V sat : saturation voltage of the transistor Q 4 V BE : base-emitter voltage of the transistors Q 5 and Q 7 . When used for other purposes, there is a problem that the voltage reduction characteristics deteriorate.
そこで、本考案は、消費電流を小とでき、且つ、減電
圧特性の良好な全波整流回路を提供することを目的とす
る。Therefore, an object of the present invention is to provide a full-wave rectifier circuit that can reduce current consumption and that has good voltage reduction characteristics.
（ニ）課題を解決するための手段 本考案は、前記問題点を解決する為になされたもので
あり、一方に基準電圧が印加され且つ他方に入力電圧が
印加される第１の差動増幅器と、入力及び動作電流源が
前記第１の差動増幅器の入力及び動作電流源と共通接続
された第２の差動増幅器と、前記入力電圧を電流交換す
る抵抗と、前記第１の差動増幅器の出力電流を制御する
第１の制御トランジスタと、前記第２の差動増幅器の出
力電流を制御すべく、前記第１の制御トランジスタと相
補的に動作する第２の制御トランジスタと、前記入力電
圧の変化に応答する前記第１及び第２の制御トランジス
タの出力電流に基づいて、前記入力電圧の全波整流を行
う整流回路と、を備えたことを特徴とする。(D) Means for Solving the Problems The present invention has been made to solve the above problems, and a first differential amplifier in which a reference voltage is applied to one side and an input voltage is applied to the other side. A second differential amplifier having an input and operating current source commonly connected to the input and operating current source of the first differential amplifier; a resistor for exchanging the input voltage; and a first differential amplifier. A first control transistor for controlling the output current of the amplifier; a second control transistor that operates complementarily to the first control transistor to control the output current of the second differential amplifier; and the input And a rectifier circuit that performs full-wave rectification of the input voltage based on output currents of the first and second control transistors that respond to changes in voltage.
（ホ）作用 本考案によれば、全波整流回路において、消費電流が
従来に比べて小となり、更に、減電圧特性も従来に比べ
て良好となる。(E) Operation According to the present invention, in the full-wave rectifier circuit, the current consumption becomes smaller than the conventional one, and the voltage reduction characteristic becomes better than the conventional one.
（ヘ）実施例 本考案の詳細を図面に従って具体的に説明する。(F) Embodiment The details of the present invention will be specifically described with reference to the drawings.
第１図は、本考案回路を示す回路図である。 FIG. 1 is a circuit diagram showing the circuit of the present invention.
第１図において、トランジスタQ1,Q2は第１の差動増
幅器を構成し、トランジスタQ1のベースには基準電圧V
refが印加され、トランジスタQ2のベースには抵抗Ｒを
介した入力電圧VINが印加される。トランジスタQ3,Q4は
第２の差動増幅器を構成し、該トランジスタQ3,Q4のベ
ース及びエミッタは前記トランジスタQ1,Q2のベース及
びエミッタと共通接続される。ここで、トランジスタ
Q2,Q4のベースは、トランジスタQ14,Q15のエミッタ出力
が全帰還されて仮想接地点とされ、更に、入力電圧VIN
は、抵抗Ｒによって電流変換されてトランジスタQ2,Q4
のベースに印加される。これより、抵抗Ｒを流れる電流
はVIN/Rで表されることになるが、該電流は、仮想接地
点に対する入力電圧VINの極性に応じて、流れる方向が
異なる。つまり、入力電圧VINが基準電圧Vrefより大の
時、前記電流はトランジスタQ15に供給され、入力電圧V
INが基準電圧Vrefより小の時、前記電流はトランジスタ
Q14から供給される。従って、入力電圧VINの極性に拘ら
ず、抵抗Ｒの両端には正電圧が現れ、該正電圧がコンデ
ンサＣで平滑化され、全波整流された出力電圧VOUTが得
られる。In FIG. 1, the transistors Q 1 and Q 2 form a first differential amplifier, and the base of the transistor Q 1 has a reference voltage V
ref is applied, and the input voltage V IN via the resistor R is applied to the base of the transistor Q 2 . Transistors Q 3, Q 4 constitutes a second differential amplifier, the base and emitter of the transistor Q 3, Q 4 are commonly connected to the base and emitter of the transistor Q 1, Q 2. Where the transistor
The bases of Q 2 and Q 4 are set as a virtual ground point by fully feeding back the emitter outputs of the transistors Q 14 and Q 15 , and the input voltage V IN
Is converted into a current by a resistor R, and the transistors Q 2 and Q 4
Applied to the base of. As a result, the current flowing through the resistor R is represented by V IN / R, but the current flows in different directions depending on the polarity of the input voltage V IN with respect to the virtual ground point. That is, when the input voltage V IN is greater than the reference voltage V ref , the current is supplied to the transistor Q 15 and the input voltage V IN
When IN is less than the reference voltage V ref , the current is
Supplied from Q 14 . Therefore, a positive voltage appears across the resistor R regardless of the polarity of the input voltage V IN, the positive voltage is smoothed by the capacitor C, and the full-wave rectified output voltage V OUT is obtained.
以下、具体的動作について説明する。 The specific operation will be described below.
入力電圧VINが基準電圧Vrefより大となった場合、ト
ランジスタQ2,Q4のベースが負帰還によって仮想接地と
なっている為、抵抗Ｒで電流変換された電流は、トラン
ジスタQ15のエミッタ電流として供給されることにな
る。トランジスタQ15のベースには、エミッタ電流に応
じたベース電流が発生し、このベース電流は、トランジ
スタQ9,Q11,Q12を通じ、第１の差動器を構成するトラン
ジスタQ1,Q2の出力から供給される。この時、トランジ
スタQ10,Q14はオフである。一方、入力電圧VINが基準電
圧Vrefより小の場合、抵抗Ｒで電流変換された電流は、
トランジスタQ14から供給されることになる。トランジ
スタQ14のベースには、エミッタ電流に応じたベース電
流が発生し、このベース電流は、トランジスタQ10を通
じ、第２の差動増幅器を構成するトランジスタQ3,Q4の
出力から供給される。この時、トランジスタQ9,Q11,
Q12,Q15はオフである。こうして、トランジスタQ9,Q10
は相補的に動作し、入力電圧VINに応じた電流がトラン
ジスタQ19のコレクタに流れ、該コレクタ電流に応じた
抵抗Ｒの両端の電圧がコンデンサＣによって平滑化さ
れ、これより、全波整流された出力電圧VOUTが得られ
る。When the input voltage V IN becomes higher than the reference voltage V ref , the bases of the transistors Q 2 and Q 4 are virtually grounded by the negative feedback, and the current converted by the resistor R is the current of the transistor Q 15 . It will be supplied as an emitter current. The base of the transistor Q 15, the base current is generated in accordance with the emitter current, the base current, transistor Q 1, Q 2, which through the transistors Q 9, Q 11, Q 12 , constituting the first differentiator Is supplied from the output of. At this time, the transistors Q 10 and Q 14 are off. On the other hand, when the input voltage V IN is smaller than the reference voltage V ref , the current converted by the resistor R is
It will be supplied from transistor Q 14 . The base of the transistor Q 14, a base current is generated in accordance with the emitter current, the base current through the transistor Q 10, supplied from the output of the transistor Q 3, Q 4 constituting a second differential amplifier . At this time, the transistors Q 9 , Q 11 ,
Q 12 and Q 15 are off. Thus, transistors Q 9 and Q 10
Operate in a complementary manner, a current corresponding to the input voltage V IN flows through the collector of the transistor Q 19 , and the voltage across the resistor R corresponding to the collector current is smoothed by the capacitor C. The output voltage V OUT is obtained.
尚、無信号時、トランジスタQ9,Q10には、負帰還によ
り定まる微小電流しか流れない。Incidentally, when there is no signal, only a minute current determined by the negative feedback flows through the transistors Q 9 and Q 10 .
以上より、第１図回路によれば、入力電圧VINのレベ
ルの変化に応じた電流消費を行い、且つ、無信号時、ト
ランジスタQ9,Q10には、負帰還により定まる微小電流し
か流れない為、従来に比べて消費電流を小とできる。ま
た、電源電圧VCCは、 VCC＝Vref＋Vsat＋VBE Vsat：トランジスタQ10の飽和電圧 VBE：トランジスタQ14のベース・エミッタ間電圧 となり、減電圧特性が従来に比べてVBEだけ改善された
ことになる。更に、第１図回路は、IC化に適する。As described above, according to the circuit shown in FIG. 1, current consumption is performed according to the change in the level of the input voltage V IN , and when there is no signal, only a small current determined by the negative feedback flows through the transistors Q 9 and Q 10. Since it does not exist, the current consumption can be made smaller than in the past. The power supply voltage V CC is, V CC = V ref + V sat + V BE V sat: transistor saturation voltage V BE of Q 10: transistor base-emitter voltage next to Q 14, V compared to reduced voltage characteristics prior BE Only improved. Further, the circuit shown in FIG. 1 is suitable for being integrated into an IC.
（ト）考案の効果 本考案によれば、入力電圧の変化に応じた電流消費を
行い、且つ、無信号時、第１及び第２の制御トランジス
タに伴う電流消費を無視できる為、消費電流を低減する
ことが可能となり、更に、減電圧特性の改善も可能とな
る等の利点が得られる。(G) Effect of the Invention According to the present invention, the current consumption according to the change of the input voltage is performed, and the current consumption due to the first and second control transistors can be ignored when there is no signal. It is possible to reduce the voltage, and further, it is possible to improve the reduction voltage characteristic.
第１図は本考案回路を示す回路図、第２図は従来回路を
示す回路図である。 （１）（２）……定電流源。FIG. 1 is a circuit diagram showing a circuit of the present invention, and FIG. 2 is a circuit diagram showing a conventional circuit. (1) (2) …… Constant current source.
Claims (3)
の入力に入力電圧が印加される第１の差動増幅器と、 入力及び動作電流源が前記第１の差動増幅器の入力及び
動作電流源と共通接続された第２の差動増幅器と、 前記入力電圧を電流変換する抵抗と、 前記第１の差動増幅器の出力電流を制御する第１の制御
トランジスタと、 前記第２の差動増幅器の出力電流を制御すべく、前記第
１の制御トランジスタと相補的に動作する第２の制御ト
ランジスタと、 前記入力電圧の変化に応答する前記第１及び第２の制御
トランジスタの出力電流に基づいて、前記入力電圧を行
う整流回路と、 を備え、前記第１及び第２の制御トランジスタの出力電
流に基づく電流が前記第１及び第２の差動増幅器の他方
の入力に全帰還されることを特徴とする全波整流回路。1. A first differential amplifier having a reference voltage applied to one input and an input voltage applied to the other input, and an input and operating current source for the input and operation of the first differential amplifier. A second differential amplifier commonly connected to a current source; a resistor for converting the input voltage into a current; a first control transistor for controlling an output current of the first differential amplifier; and a second difference A second control transistor that operates complementarily to the first control transistor to control the output current of the dynamic amplifier; and output currents of the first and second control transistors that respond to changes in the input voltage. A rectifier circuit that performs the input voltage based on the input voltage, and the current based on the output currents of the first and second control transistors is fully fed back to the other input of the first and second differential amplifiers. Full wave characterized by Flow circuit.
スタと接続される第１の電流ミラー回路と、前記第２の
制御トランジスタと接続される第２の電流ミラー回路と
を含んで成ることを特徴とする請求項（１）記載の全波
整流回路。2. The rectifier circuit includes a first current mirror circuit connected to the first control transistor, and a second current mirror circuit connected to the second control transistor. The full-wave rectifier circuit according to claim 1, wherein
電流ミラー回路を構成するトランジスタのベース・エミ
ッタ間電圧と、前記第２の制御トランジスタの飽和電圧
とを加算した値で定まることを特徴とする請求項（２）
記載の全波整流回路。3. A minimum operating voltage is determined by a value obtained by adding a reference voltage, a base-emitter voltage of a transistor forming the second current mirror circuit, and a saturation voltage of the second control transistor. Claim (2) characterized by
Full wave rectifier circuit described.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989134160U JPH0810973Y2 (en) | 1989-11-17 | 1989-11-17 | Full wave rectifier circuit |
| KR2019900017633U KR0112748Y1 (en) | 1989-11-17 | 1990-11-16 | Full wave rectifying circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989134160U JPH0810973Y2 (en) | 1989-11-17 | 1989-11-17 | Full wave rectifier circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0373023U JPH0373023U (en) | 1991-07-23 |
| JPH0810973Y2 true JPH0810973Y2 (en) | 1996-03-29 |
Family
ID=15121865
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989134160U Expired - Lifetime JPH0810973Y2 (en) | 1989-11-17 | 1989-11-17 | Full wave rectifier circuit |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH0810973Y2 (en) |
| KR (1) | KR0112748Y1 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61148903A (en) * | 1984-12-21 | 1986-07-07 | Rohm Co Ltd | Detection circuit |
| JPS61198065A (en) * | 1985-02-28 | 1986-09-02 | Nec Corp | Rectifying circuit |
-
1989
- 1989-11-17 JP JP1989134160U patent/JPH0810973Y2/en not_active Expired - Lifetime
-
1990
- 1990-11-16 KR KR2019900017633U patent/KR0112748Y1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| KR910010048U (en) | 1991-06-29 |
| JPH0373023U (en) | 1991-07-23 |
| KR0112748Y1 (en) | 1998-04-18 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |