JPH0814784B2 - Print control device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printer device, and more particularly to a print control device having a frame memory for storing image signal data.

[Prior art]

A printer is an output device for printing characters on paper, receives character information for normal printing from an electronic computer or a recording medium, converts it into print data inside the printer, and prints it on output paper. FIG. 4 is a circuit block diagram of a conventional print control device. In the figure, a character code, characteristic data and the like are sent to the printer from a host computer (not shown) or the like. Among them, the coat data is input to the character pattern generator 1 via a code buffer (not shown) under the control of the main controller, and the characteristic data is input to the character pattern generator 1 via a parameter buffer (not shown).
To enter. The coat data is the serial data generator 2 in the character pattern generator 1 and the character generator RO.
The pattern is converted by M3 and output to the bit shift circuit 4. The bit shift circuit 4 is composed of an AND gate 5, a shift register 6, a bit shift control circuit 7, and a frame memory write control circuit 8. The above dot pattern data is a data enable (DEN) signal which will be described later for each bit. And input to AND gate 5. The input serial data (dot pattern data) is valid only when the data enable signal is “high level” and invalid when it is “low level”, for example. The input serial data is ANDed with the data enable signal (DEN signal) by the AND gate 5 and output to the shift register 6.

The bit shift control circuit 7 shifts (SHIFT) in synchronization with the clock signal (CLK) output from the main control unit described above.
The signal is output to the shift register 6. Shift register 6
Generates write data by performing bit shift according to the shift signal. The bit shift control circuit 7 sends a set request (SETREQ) signal to the frame memory write control circuit 8 when the shift register 6 has write data. When this set request signal is supplied, the frame memory write control circuit 8 sends a write address and a write request signal to the frame memory section 9 and writes write data to the frame memory 9.

On the other hand, if the write data is not yet complete at the time when the predetermined number of bits of the serial data are input, the data enable signal (DEN signal) is input from the character size control circuit 10 to the shift register 6. Disable the serial data input of. Then, the shift operation is continued until the blank bit data is prepared in the shift register 6 by the clock signal and the shift signal. To write data to the frame memory unit 9, an OR circuit (not shown) logically sums the internal data of the frame memory with the write data,
It is overwritten. When overwriting data in the frame memory unit 9, if the write data is blank data, the data in the frame memory does not change. In this manner, the dot pattern data for one page is sequentially written in the frame memory 9, and the data for one page thus written is output to the printing unit (not shown) under the control of the main control unit. Is printed on the paper.

[Problems of conventional technology]

However, in the conventional print control device as described above, the black print data (and the blank data) input to the shift register 6 is bit-shifted, converted into predetermined parallel data (write data), and set by the set request signal. All data is written in the frame memory unit 9.

Therefore, since the address of the frame memory unit 9 is designated and the write data is written regardless of the presence or absence of the black print data and the blank data for each request signal, it takes time to access the frame memory unit 9 and to write the data. Then
The data processing time was long.

[Object of the Invention]

In view of the above-mentioned conventional drawbacks, the present invention shortens the data processing time by detecting whether or not the dot data exists in the write data, and if the dot data does not exist, the writing of a predetermined bit is omitted. It is an object of the present invention to provide a print control device capable of achieving the above.

[Main points of the invention]

In order to achieve the above object, the present invention provides a print control device comprising a writing means for writing image data input serially bit by bit into a storage means for storing two-dimensional image data collectively for every predetermined bit, The writing means is 1
Image data is input bit by bit and black print data detecting means for detecting that black print data is not included for each predetermined amount of the image data, and the image according to the detection signal detected by the black print data detecting means It is characterized by comprising a writing omission means for omitting writing of the predetermined amount of image data in a storage means for storing data.

Example of Invention

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a circuit block diagram of the entire system including the print controller of this embodiment. In the figure, for example, data for one page of paper to be printed is input in the form of character codes from the host device such as a host computer to the in-printer reception buffer 12. In addition to the character code, the character buffer, line feed, character size, and other characteristic data are also received in the receive buffer.
Enter in 12. Regarding the character code and the characteristic data, the character code and the characteristic data are input-controlled by the main control unit 13, the character code is stored in the code buffer 14, and the characteristic data is the print control device according to the conversion ROM in the main control unit 13. After being converted into the control parameter of, the data is stored in the parameter buffer 15. The character codes stored in the code buffer 14 are output to the character pattern generator 16 for each character code under the control of the main controller 13.

As shown in FIG. 1, the character pattern generator 16 is composed of a serial data generator 17, a CG-ROM (hereinafter, referred to as CG) 18, a character size control circuit 19, and a bit shift circuit 20.
The character code output for each character code described above is output to the serial data generator 17, and the serial data generator 17 reads the input character code to the CG 18. The CG 18 stores character pattern data corresponding to a large number of character codes, and outputs dot pattern data corresponding to an input character code to the serial data generator 17. The serial data generation unit 17 synchronizes the dot pattern data that has been further converted with the clock signal output from the main control unit 13 to the serial data generation unit 17, and performs a bit shift circuit for each bit.
Output to 20.

The bit shift circuit 20 includes an AND gate 21, a blank data detection circuit 22, a shift register 23a, a register 23b, a bit shift control circuit 24, and a frame memory control circuit 25. The 1-bit serial data output from the serial data generator 17 is output to the AND gate 21. In the AND gate 21, the character size control circuit 19 described later
Only when the DEN signal is input as a high signal, the serial data is output to the blank data detection circuit 22 and the shift register 23a.

The shift register 23a inputs the serial data (SD) in 1-bit units in synchronization with the clock signal (CLK) sent from the main control unit 13, and sequentially converts the serial data (SD) into 16-bit parallel write data. In addition, 1 of the shift register 23a
The 6-bit parallel data is output to the register 23b in synchronization with a request signal described later.

On the other hand, the blank data detection circuit 22 described above is composed of the specific circuit shown in FIG. In the figure, the above-mentioned serial data is input to the AND gate G ₁ together with a shift signal described later. Then, for example, when the shift signal is "high", Shiruaru data described above is inputted from the AND gate G ₁ to the terminal of the flip-flop 26 outputs a high signal from the Q terminal of the flip-flop 26 in synchronization with a clock signal , Input this high signal to the OR gate G ₂ . The OR gate G ₂ and the AND gate G ₃ form a memory circuit, and when the clear signal (CLR) input from the bit shift control circuit 24 described later is “high level”, for example, the “Q” terminal of the flip-flop 26 is The "high level" output is maintained. That is, the output of a predetermined bit "1" in the serial data (16-bit) signal AND gate G ₃ if it contains (black print data) to be input is kept at the "high level". This output signal of the AND gate G ₃ is output as a dot detection signal to the frame memory write control circuit 25 described later. The output of the AND gate G ₃ described above is outputted through the inverter to the AND gate G _4, data enable (DEN) signal to be input via the inverter to the same AND gate G _4, and inputs via the inverter G ₅ According to the shift signal, it is output to the bit shift control circuit 24 as a shift stop request signal which will be described in detail later.

On the other hand, the bit shift control circuit 24 is a circuit that outputs the above-described shift signal, clear signal, set request signal, and control signal c to the character size control circuit 19. A clock signal, a DEN signal, a shift stop signal, and a control signal A from the frame memory write control circuit 25 are input to the bit shift control circuit 24, and the bit shift control circuit 24 uses the input clock signal as a basis. Count,
When the shift stop request signal is not input, the shift signal is output to the AND gate G ₁ and the inverter G ₅ of the blank data detection circuit 22, the shift register 23a, and the serial data generator 17 in synchronization with the clock signal. Then, when 16 pulses of the clock signal are input corresponding to 1 word 16-bit serial data to be written to the shift register 23a, the set request signal is sent to the frame memory write control circuit 25,
Output to register 23b. When the shift stop request signal is input, the output of the shift signal to the AND gate G ₁ of the blank data detection circuit 22, the serial data generator 17, and the shift register 23a is stopped, and at the same time the set request signal is framed. The data is output to the memory write control circuit 25 and the register 23b. Further, the clear signal is the AND gate G of the blank data detection circuit 22 when the control signal A input for a predetermined time after the above-mentioned request signal is input.
₃ , output to the shift register 23a.

The frame memory write control circuit 25 inputs the dot detection signal from the AND gate G ₃ of the blank data detection circuit 22 described above, the set request signal from the bit shift control circuit 24, and the main control unit 13 to the frame memory. The initial value of the address for writing data is input in the section 27. When the set request signal is input, the frame memory write control circuit 25 outputs the write request signal to the frame memory unit 27 in synchronization with the clock signal if the dot detection signal is input. The write request signal is sent to the frame memory unit 27.
Then, for example, it is output after confirming the control signal B output when the writing of the previous data is completed. After outputting the write request signal, the frame memory write control circuit 25 outputs the write address data to the frame memory unit 27, and then outputs the control signal A to the bit shift control circuit 24.

On the other hand, the character size control circuit 19 receives character size data from the parameter buffer 15 and a bit shift control circuit 24 receives a control signal (ready signal) c under the control of the main control unit 13. The character size data described above is data that specifies the character size to be written in the frame memory unit 27, and is input to the serial data generation unit described above. For example, the data of this character size is 24 dots vertically,
It is vertical and horizontal data that forms characters in dot units such as horizontal 24 dots or vertical 32 dots, horizontal 32 dots. Then, while the control signal c is not input from the bit shift control circuit 24, if 16 clock signals (one word) are input, the control signal E is output to the serial data generator 17, and the serial data generator 17 outputs the control signal E as described above. AND gate 2 for a new word in the character data converted to dot pattern data
Output to 1. When the control signal C is input from the bit shift control circuit 24, the control signal E is output to the serial data generator 17 without counting 16 pulses of the clock signal, and the serial data generator 17 outputs the dot pattern as described above. The new one word of the character data converted into data is output to the AND gate 21.

Further, for example, when the character size is vertical 24 dots × horizontal 24 dots, when the horizontal 24 dots are divided into 16 dots (1 word) as described above, it becomes 16 dots + 8 dots. Therefore,
After counting the first 16 dots, 8 dots after 16 dots of the next word become blank data. At this time, the DEN signal is output to the AND gate 21, the bit shift control circuit 24, and the AND gate G ₄ of the blank data detection circuit 22 in synchronization with the clock signal.

Although described before and after, the frame memory section 27 is composed of a memory area corresponding to a print area on a print sheet (not shown), and the above-mentioned write request signal is input from the frame memory write control circuit 25 to write address. Is specified, 16-bit (1 word) write data is input from register 23b and data (pattern data) is sent to the specified address.
Write in.

The operation of the print control device of the present embodiment having the above circuit configuration will be described below.

First, code data input from a host computer (not shown) is input to the serial data generator 17 via a reception buffer (not shown) and converted into a dot pattern there. Further, the dot pattern data is serially input to the AND gate 21. The AND gate 21 outputs the print data to the AND gate G ₁ in the blank data detection circuit 22 when the enable signal output when the print data is valid data is input at the same time.

The serial data is also supplied to the shift register 23a, and the serial data input to the AND gate G ₁ and the shift register 23a is sequentially shifted by the shift signal from the bit shift control circuit 24. During this period, the bit shift control circuit 24 checks whether the shift stop request signal is input. That is, unless the signal output from the AND gate G _{4 of} FIG. 3 described later is input into a predetermined bit (16 bits), the bit shift control circuit 24 shifts the shift register 23.
When the creation of 16-bit write data by a is completed, the shift signal (SHIFT) is set to, for example, “low level”, the serial data input from the serial data generator 17 is interrupted, and the set request signal is set to, for example, “low level”. The level is changed from "level" to "high level" and added to the frame memory write control circuit 25. When the set request signal is applied, the frame memory writing control circuit 25 sets the control signal A to, for example, a high level, and further checks the dot detection signal described above. If, for example, a dot is detected (high level), the frame memory unit 27.
The write request signal is output to. When a write request signal is added,
In the frame memory unit 27, the control signal B is set to, for example, a high signal, and the write data is overwritten from the frame memory write control circuit 25 to the corresponding address in the frame memory unit.
When the storage of the write data to the corresponding address in the frame memory unit 27 is completed, the frame memory unit 27 outputs the control signal B.
Is set to, for example, a low level to notify the frame memory write control circuit 25 that the writing of the write data to the frame memory unit 27 is completed. When the control signal B becomes low level, the frame memory write control circuit 25 updates the write address and then sets the control signal A to low level as well to wait for the next set request signal. On the other hand, when the dot detection signal is not detected (low level) when the set request signal is applied, the write request to the frame memory unit 27 is not output, and the control signal A is immediately changed to low level after updating the write address. And waits for the next set request signal. That is, when the DEN signal becomes low level during the shift and the print data does not include the print dot, the blank data detection circuit 22 outputs the shift stop request. When the shift stop request is added, the bit shift control circuit stops the shift and outputs a set request signal. At this time, if the control signal A is at the high level as described above, it waits without outputting the set request signal until it becomes the low level. After outputting the set request signal, the bit shift control circuit 24 shifts to the next operation. That is, since the DEN signal is at the low level, the control signal C is set to, for example, the low level (READY) and the DEN signal is set to the high level, for example.

As described above, the DEN signal is a signal output by the character size control circuit 19 in correspondence with the remaining bits in one word to be blank data. In the character size control circuit 19, when the control signal C is in the ready state and the DEN signal is at a low level, the control signal E is output to instruct the serial data generator 17 to input one word of serial data. In other words, when the data enable signal (DEN signal) becomes low level while the 16-bit write data is being created, if there is a print dot in the write data up to that point, the shift is performed by the specified number of bits. After continuing, the data is written in the frame memory unit 27, and if the print dot is not included, the data is not written in the frame memory unit 27. Therefore,
According to this process, if the print data does not include the print dots, the creation of the remaining write data is stopped, the writing to the frame memory unit 27 is omitted, and the process shifts to the next process.
A control signal C (ready signal) is output to output new 1-word serial data from the serial data generator 17. As described above, when the shift stop request is input, the control signal C (ready signal) is output, and the E signals are sequentially output to the serial data generation unit 17, thereby increasing the character code processing speed as compared with the conventional case. .

Further, when there is no blank data in the serial data, the flip-flop 26 in the blank data detection circuit 22
Then, it is always checked whether or not the print dot is included in the serial data, and if no print signal is included, the dot detection signal is not output to the frame memory write control circuit 25. The frame memory write control circuit 25 confirms this when the predetermined bit clock is counted. If “no dot detection” is detected, the write request signal to the frame memory unit 27 is not issued, and the bit shift control circuit is used. And outputs a ready signal to the character size control unit 19. The subsequent processing is the same as that described above, and in this case as well, the speed of the entire writing to the frame memory unit 27 can be increased.

The pattern data written in the frame memory unit 27 at high speed as described above is controlled by the main control unit 13,
It is sent to the printing unit 31 via the video signal control unit 30.

〔The invention's effect〕

As described above in detail, according to the present invention, the number of accesses to the frame memory can be reduced by omitting the writing of blank data into the frame memory. Further, when it is detected that the final write data becomes blank data while the write data is created by the bit shift, the conversion to the write data by the bit shift after that can be stopped. Therefore, the data processing time can be shortened.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit block diagram of a print control device of the present invention, FIG. 2 is a system configuration diagram including the print control circuit of this embodiment, and FIG. 3 is a blank data detection circuit. 4 is a circuit block diagram of a conventional print control circuit and the like. 22 …… Blank data detection circuit, 23a …… Shift register, 2
3b …… Register, 24 …… Bit shift control circuit, 25 ……
Frame memory write control circuit.

Claims (1)

[Claims] 1. A print control apparatus comprising a writing means for writing image data serially input bit by bit into a storage means for storing two-dimensional image data collectively for every predetermined bit, wherein the writing means comprises: Image data is input bit by bit and black print data detecting means for detecting that black print data is not included for each predetermined amount of the image data, and the image according to the detection signal detected by the black print data detecting means A printing control device, comprising: a writing omission means for omitting writing of the predetermined amount of image data in a storage means for storing data.