JPH08166409A - Waveform storage - Google Patents

Abstract

(57) [Abstract] [Purpose] High-speed SRA in the memory division waveform acquisition function in waveform storage devices such as digital oscilloscopes.
It is an object of the present invention to use a frame memory for image that is cheaper than M, to enable pre-trigger acquisition, and to shorten the dead time between each divided waveform acquisition. A waveform storage device including an AD conversion circuit, a frame memory arranged in two stages, a front stage and a rear stage, a control circuit for controlling the frame memory, a time base circuit for outputting a sample clock, and a sample control circuit for controlling the number of samples.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement of a waveform storage system of a waveform storage device such as a digital oscilloscope.

[0002]

2. Description of the Related Art Conventionally, oscilloscopes have been used for observing waveforms of various data, and they have been indispensable and useful especially for research and development and production of electronic devices, but there is one aspect that waveforms cannot be stored. However, as is well known, along with the development of digital technology, a digitized oscilloscope has been developed, and a large capacity of memory has enabled a large amount of waveform storage. Among them, the waveform storage device stores the analog input signals of various data after digital processing and stores them, and makes it possible to observe the stored waveforms and other applications in combination with a display device or a computer. Is.

For example, in a digital oscilloscope, FIG.
As shown in, there is a function called memory division collection in which a large-capacity memory is divided as an acquisition memory and an input signal is sequentially stored in memory blocks divided for each trigger. This memory division collection is, as shown in FIG. 3, dividing the memory into n (several divisions to several thousands divisions) and triggering the input signal T
The number of waveforms obtained by intermittently dividing each S is collected.

A large-capacity memory is required to perform such memory division data collection. This point, SR
AM has a large capacity, but writing and reading cannot be performed at the same time, and even if a high-speed large-capacity SRAM is used, the dead time of waveform acquisition (waveform acquisition from the end of one waveform acquisition to the next 1)
There is a large defect of 00 μs (an example of the maximum value). Furthermore,
Such SARMs are very expensive.

On the other hand, when a relatively inexpensive image frame memory is used as the acquisition memory, the waveform can be collected only immediately after the trigger because of the structure of the image frame memory. That is, a plurality of waveforms (pre-trigger) before the trigger cannot be divided and collected. Since the image frame memory is a serial storage system, in order to store the waveform of the first division and the waveform of the second division in order, writing to the memory is started by the trigger signal and a predetermined number of writings are performed. This is because there is no choice but to stop and wait for the next trigger. Therefore, in the case of the pre-trigger, only the data for the first one waveform can be obtained.

[0006]

In the above-mentioned prior art, even if a high speed SRAM is used, for example, the dead time of waveform acquisition is large, and the high speed SRAM is very expensive. Further, when a relatively inexpensive frame memory for images is used, there is a drawback that waveform acquisition by a pre-trigger cannot be performed.

A first object of the present invention is to realize memory division acquisition capable of pre-triggering in an image frame memory.

A second object of the present invention is to realize memory division acquisition with a small dead time for waveform acquisition.

[0009]

According to the present invention, in order to achieve the above object, the image frame memory has a two-stage structure including a front stage and a rear stage, and the latest waveform is collected in the frame memory in the front stage.
In the latter part, the waveform data collected in the first part is written sequentially.

[0010]

The operation of the present invention will be described. The front-stage frame memory is controlled so that it can be written and read in a ring shape with the memory capacity of one division, and the rear-stage sequentially writes the waveform data of the front-stage frame memory from address 0. When the previous frame memory has stopped collecting waveform data for one division and then stopped, the oldest data in the previous frame memory is read out when the next sampling is started, and is written into the subsequent frame memory, and at the same time Write the new waveform data to the oldest data. That is, the write address follows the read address of the preceding frame memory, and new waveform data is written at the read address.

In this way, the preceding frame memory operates in a ring shape with a certain memory length. When the former memory writes new data for the memory length, the old waveform data is written in the latter frame memory. As described above, the memory divided acquisition waveform is stored in the subsequent frame memory by repeating the number of memory divisions.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention in a digital oscilloscope. Reference numeral 11 is an input circuit, which is composed of an attenuator, an amplifier and the like. 1 is A
The input signal (observed signal) adjusted to an appropriate level by the input circuit 11 in the / D conversion circuit becomes digital waveform data in this AD conversion circuit 1 and is written in the frame memory 2 in the preceding stage. The frame memories 2 and 3 form an acquisition memory. The write address and the read address of the frame memory 2 are incremented by the write clock (write clock) and the read clock (read clock) output from the frame memory control circuit 4, respectively. Further, it is reset to address 0 by the write reset and read reset signals.

FIG. 2 is a diagram for explaining the operation of the frame memory 2.
As shown in FIG. 2, the frame memory 2 is incremented so that the write address follows the read address, and in this example, it is reset after 999th address and returns to 0th address, and is a ring memory of 1000 words. Here, if the address to be reset is changed, the memory operates as a ring memory having an arbitrary number of words.

Next, operations such as address control of the preceding stage frame memory 2 will be described. Frame memory 2
9 is as shown in FIG. 9, 211 is an input buffer for digital input data, 212 is a memory, 213 is an output buffer, 214 is a write address counter, and 215 is a read address counter. A feature of the frame memory is that it has a built-in write address counter 214 and a read address counter 215, and each operates independently in serial by a write clock or a read clock. That is, it is possible to read while writing. In the write clock operation of the frame memory, the write address counter 214 operates according to the write clock,
A write address is designated for the memory 212, the input data is transmitted to the memory 212 through the input buffer 211, and the data is written. When the write clock is input again, the write address counter 214 causes the memory 21
Increment the write address of 2. In this way, the memory 212 sequentially stores time-series data. On the other hand, also in the read operation, the read address counter 215 operates similarly by the read clock to specify the read address to the memory 212, and the read data is output as output data through the output buffer 213. When the read clock is input again, the read address counter 215 increments the read address of the memory 212. In this way, the data of the memory 212 is sequentially read out in time series by the read clock.

Returning to FIGS. 1 and 2, the normal sampling by the trigger signal will be described. Time base circuit 6
Outputs a sampling clock SC under the control of starting and stopping the sample control circuit 5. When the sampling for one division is completed, the waveform data for one division is stored in the frame memory 2 (in this example, 100
0 words). However, it is uncertain at which address the write address stops, but in the example of FIG.
It stops when the newest data is written to address 1, and the oldest data is stored at address n of the read address. When the next sampling is started, as shown in FIG. 4, the waveform data of the preceding stage frame memory 2 is transferred from the address n to the addresses k, k + 1, ...
At this time, new data is sequentially written in the frame memory 2 at the same time. When the frame memory 2 writes one cycle (1000 words) of the waveform data, at that time, the transfer of the previous sample data of the frame memory 2 to the frame memory 3 is finished at the same time, so the writing to the frame memory 3 is also stopped. Next, the previous stage frame memory 2 again receives the address n
Continue sampling from the address. When the trigger signal TS is input to the sample control circuit 5, the waveform data for the next one division is collected after counting a predetermined number of samples. However, at this time, without stopping the sampling clock, the next waveform data collection is started and the waveform data for one division, which has been completely stored in the frame memory 2 as in the previous time, is transferred to the frame memory 3.

Next, the operation at the time of pre-trigger will be described. In this example, the frame memory 2 is a 1000-word ring memory. In other words, if you want to take half the pre-trigger and set the trigger position to the center of the displayed waveform,
The 00 word is first stored unconditionally, and immediately after that, the trigger can be accepted (trigger enable). This operation is shown in the sampling control flowchart of FIG.
If 500 words are stored after the trigger is generated and the storage operation is stopped, the center position of the stored 1000-word waveform becomes the trigger position. In this way, by starting the sampling to secure the waveform before the trigger and then inhibiting the reception of the trigger for the specified number of samples and controlling the number of memory after the trigger, the stored data You will be able to observe the waveform before and after. That is, the pre-trigger waveform can be observed.

However, according to the present invention, the momentary frame memory 2 when the number of memories after the trigger reaches a predetermined number in order to make it possible to continuously capture the waveform starts the next waveform storage and the waveform stored this time. To the frame memory 3 (this operation is shown in the operation flowchart of the frame memory 2 of FIG. 11 and the operation flowchart of the frame memory 3 of FIG. 12). That is, the waveform data stored this time is read from the frame memory 2 at the same time as the next waveform storage (writing). Since one word is written and one word is read, the frame memory 2 sets the next waveform data to 1
While writing 000 words, all 1000 words of the current waveform data are read from the frame memory 2 and written in the frame memory 3. As shown in FIG. 8, since the frame memory 3 writes serially without resetting the write address, if this operation is performed 1000 times, a waveform for 1000 triggers will be stored.
Specific examples of this operation are shown in FIGS. 5, 6 and 7.

FIG. 5 is an explanatory diagram of the operation of the frame memory 2 at the time of sampling the waveform of the first division. From the start of the trigger signal sampling to the sampling of the final data for 500 words after the trigger reception (input). Show.

FIG. 6 is a diagram for explaining the sampling operation of the waveform of the second division of the preceding frame memory 2 and the transfer operation of the sampling data of the waveform of the first division to the succeeding frame memory 3.

Acceptance of triggers is prohibited up to 500 words at the start of sampling the waveform of the second division (trigger hold-off), and acceptance of triggers is permitted when 500 words are sampled.

During this time, the memory 3 is operated from the sampling start of the frame memory 2 until 1000 words are sampled.
Transfer of 1000 words to.

Thereafter, if the trigger signal is not generated, the frame memory 2 repeats sampling in a ring shape. During this time, the transfer from the frame memory 2 to the frame memory 3 is not performed.

Next, when a trigger signal is input, 500 words are sampled from the trigger point. Next, as shown in FIG. 7, the frame memory 2 transfers data from the data 500 words before the trigger point to the frame memory 3 in the same manner as described above, and continues sampling of the waveform of the next third division to generate a trigger. Trigger acceptance is permitted when 500 data is sampled from the point, and sampling is continued. Thereafter, the above operation is repeated.

According to the method shown in FIGS. 5, 6 and 7, the frame memory 3 has 500 words before trigger and 5 words after trigger.
A waveform of 00 words is stored in 1000 waveforms. This is shown in FIG.

As described above, since the new waveform data can be collected in the preceding frame memory 2 and at the same time the old waveform data stored in the frame memory 2 can be transferred to and stored in the frame memory 3, the dead time between the divided waveform collections can be reduced. It can be lost. By collecting the waveform data for the number of divisions, the waveform data is sequentially stored in the frame memory 3. Further, although the frame memory is used as described above, pre-trigger is also possible.

As shown in FIG. 1, the waveform data stored in the frame memory 3 is subjected to compression such as maximum value / minimum value detection or thinning by the compression circuit 10, or is passed through without compression and read by the CPU 7. . The CPU 7 converts the waveform data into display data, transfers it to the display circuit 8, and CR
The waveform is displayed on the display 9 such as T (LCD, EL, plasma, etc). Although data compression itself is well known, in this example, waveform data of 1000 words per waveform is stored, but if the horizontal resolution of the display device is 100 words, one waveform is displayed. The waveform data must be compressed to 1/10, but at this time, if the maximum value and the minimum value are detected from the frame memory 3 every 10 data and transferred to the display device, it will be compressed to 1/10. This maximum value / minimum value detection operation is performed by the compression circuit 10.

Alternatively, the data in the frame memory 3 is 1 /
In order to thin out and display 10 data, it is necessary to skip every 10 data, but since the frame memory must be read serially, it is not possible to skip every 10 data. Therefore, every time one data is transferred to the display device, nine data in the frame memory must be read in idle and the read address must be advanced. This idle reading operation is performed by the compression circuit 10. The preceding-stage frame memory 2 arranged in the preceding stage is a frame memory in this embodiment, but it can be replaced with a FIFO memory or an image line memory.

[0029]

According to the present invention, the memory division collection function can be realized by the image frame memory which is about ⅕ the price of the high speed SRAM.

According to the present invention, it is possible to omit the address generation circuit which is essential in the SRAM. That is, if the frame memory is used, the address control circuit of the waveform memory becomes unnecessary, the circuit scale around the waveform memory can be reduced, and the control can be simplified. As a result, the waveform data recording / reproducing apparatus such as a digital storage oscilloscope can be made inexpensive, lightweight and compact.

According to the present invention, in the memory division function, it is possible to shorten the dead time (0 to several hundreds ns) between data collections of each memory division.

According to the present invention, although the image frame memory is used, the pre-trigger acquisition can be realized in the memory division function.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention.

FIG. 2 is an operation explanatory diagram of the frame memory 2 according to the embodiment of this invention.

FIG. 3 is an explanatory diagram of a memory division function.

FIG. 4 is an operation explanatory diagram of the frame memories 2 and 3 according to the embodiment of the present invention.

FIG. 5 is an operation explanatory diagram of frame memories 2 and 3 according to the embodiment of the present invention.

FIG. 6 is an operation explanatory diagram of the frame memories 2 and 3 according to the embodiment of the present invention.

FIG. 7 is an operation explanatory diagram of the frame memories 2 and 3 according to the embodiment of the present invention.

FIG. 8 is an operation explanatory diagram of the frame memory 3 according to the embodiment of this invention.

FIG. 9 is a structural diagram of a frame memory.

FIG. 10 is a sampling control flowchart according to the embodiment of the present invention.

FIG. 11 is an operation flowchart of the frame memory 2 according to the embodiment of this invention.

FIG. 12 is an operation flowchart of the frame memory 3 according to the embodiment of this invention.

[Explanation of symbols]

 1 AD conversion circuit 2 frame memory 3 frame memory 4 frame memory control circuit 5 sample control circuit 6 time base circuit 7 CPU 8 display circuit 9 indicator 10 compression circuit

Claims (4)

[Claims] 1. A waveform storage device having a memory dividing and collecting function for dividing and collecting data obtained by converting an input signal to be observed into digital data into a memory, wherein an image frame memory is serially connected to the waveform collecting memory in two stages. A waveform storage device, which is used in a stage configuration, wherein the previous stage frame memory writes new waveform data, at the same time, the previously stored data is read out and written to the subsequent stage frame memory. 2. The internal write address and read address of the preceding frame memory according to claim 1 advance at the same time,
A waveform storage device characterized in that control is performed so that read and write addresses are reset at an arbitrary address length. 3. The waveform storage device according to claim 2,
The front-stage frame memory starts the next waveform collection immediately after the completion of waveform collection for one division, and at the same time, starts the transfer of the waveform data stored in the front-stage frame memory to the rear-stage frame memory. A waveform storage device, characterized in that the preceding-stage frame memory is divided by an address length with an arbitrary address length as a unit and the waveform data from the preceding-stage frame memory is stored by the number of divisions. 4. An input circuit for converting an observed input signal to an appropriate level, an A / D conversion circuit for converting the observed input signal level-converted by the input circuit into digital data, and the A / D. A front-stage frame memory that stores the digital data of the conversion circuit, a rear-stage frame memory that stores the digital data read from the front-stage frame memory, and read / write of digital data between the rear-stage frame memory and the front-stage frame memory. A frame memory control circuit for controlling, a trigger circuit for generating a trigger signal in response to an observed input signal from the input circuit, and a sample control signal for the frame memory control circuit in response to a trigger signal from the trigger circuit. A sample control circuit to be supplied, the sample control circuit, the frame memory, and the A / D converter. A time base circuit that supplies a clock signal to the exchange circuit, a CPU that controls at least the time base circuit, the sample control circuit, and the frame memory control circuit, and the digital data stored in the subsequent frame memory as display data. Digital oscilloscope characterized by having a display circuit for processing and storing as