JPH0821592B2 - Integrated circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital integrated circuit, and more particularly to an integrated circuit which selects and uses one of a plurality of oscillator circuits for an internal clock.

[Conventional technology]

Conventionally, in an integrated circuit incorporating an oscillation circuit for a system clock, oscillation is performed by connecting an oscillator to a terminal drawn from the oscillation circuit, and the oscillation signal is used as an internal system clock. In addition, when performing synchronous operation with multiple integrated circuits or to reduce the number of oscillators used, the clock output of other integrated circuits can be output through the terminals that connect the oscillators without using the oscillator circuit of the integrated circuit. There is also a usage method of supplying.

[Problems to be Solved by the Invention]

The conventional integrated circuit described above must be applicable to either method of use. However, an integrated circuit having a plurality of oscillation circuits, which selects one of the oscillation circuits according to its internal state and uses the signal as a system clock, cannot perform a synchronous operation with other integrated circuits. In particular, it is difficult to operate other chips with a common clock depending on the selection of the oscillation circuit of the integrated circuit.

An object of the present invention is to eliminate the above drawbacks and to provide an integrated circuit in which an external clock from an oscillation terminal can be synchronized and used as a system clock and an oscillation circuit used can be externally monitored. .

[Means for solving the problem]

According to the configuration of the present invention, a plurality of oscillation circuits, a selection register for instructing which one of the oscillation outputs of these oscillation circuits is selected, and one of the oscillation outputs by the instruction of the selection register.
A first gate means for selecting one of them as a system clock according to a switching signal for switching between an external clock and an internal clock regardless of the contents of the selection register. A second gate circuit for selecting an output signal of the circuit as a system clock; and a third gate circuit for outputting the contents of the selection register according to the switching signal from an external clock input terminal of an oscillation circuit other than the first oscillation circuit. And having.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram illustrating an embodiment of the present invention.
The integrated circuit of this embodiment includes a first oscillator circuit 10, a second oscillator circuit 20, oscillator connection terminals 1 and 3 of these oscillator circuits 10 and 20, oscillator connection terminals and external clock input terminals 2 and 4, Transmission gates 11,21,80, AND gates 51,52, OR gate 5
4, HAND gate 60, inverter 70, latch 40. Here, the latch 40 is used as an example of the selection register, but any circuit corresponding to a register capable of instructing which of the oscillation outputs is selected may be used.

The first oscillator circuit 10 is connected to the oscillator connection terminal 1 and the oscillator connection terminal 2 via the transmission gate 11, and the oscillator connection terminal 2 simultaneously serves as one input of the AND gate 51 and is connected to the AND gate 51. The output of the HAND gate 60 is input to the other input. The second oscillator circuit 20 is connected to the oscillator connection terminal 3 and the oscillator connection terminal 4 via the transmission gate 21, and the oscillator connection terminal 4 simultaneously serves as one input of the AND gate 52 and the transmission gate 80. The signal that has passed through the transmission gate 80 becomes the input of the HAND gate 60 and is connected to the output of the latch 40. AND gate 5
A switching signal between the normal state and the external clock input state is input from the switching terminal 8 to the remaining inputs of 2. The outputs of the AND gates 52 and 51 become the inputs of the OR gate 54, and the output of the OR gate 54 becomes the system clock in the integrated circuit.

In the normal state, the latch 40 holds the content for selecting which one of the oscillation circuits 10 and 20 is used as the system clock. Done by part.

The switching signal with the external clock in the normal state is generated in another part (not shown) of the integrated circuit, and the gate inputs of the transmission gates 11 and 21 and the AND gate 52 and the NAND gate 6 are provided.
0, input to the inverter 70, and the output of the inverter 70 is input to the gate of the transmission gate 80.

In this circuit, the switching signal is at a high level in the normal state, and the transmission gates 11 and 21 are in the conductive state. Further, the switching signal is inverted by the inverter 70, and the transmission gate 80 is in a non-conductive state.

When an oscillator is connected between the oscillator connection terminals 1 and 2 and between the terminals 3 and 4 in this state, the oscillation circuits 10 and 21 start oscillating at a frequency according to the oscillator. Now, when the output of the latch 40 is high level, both inputs of the NAND60 become high level,
The output of HAND60 becomes low level, one input of AND51 becomes low level, and the signal of the oscillation circuit 10 is not input to the OR gate 54.

The oscillation signal of the oscillation circuit 20 becomes the system clock from the output of the AND52 through the OR54 because the other input of the AND52 is at the high level. Also, when the output of the latch 40 is low level, the AND52 output is fixed to low level and NAN
Since the output of D60 is fixed at the high level, the oscillation circuit 10
Signal is supplied as a system clock through AND51 and OR54. Further, the switching timing of the latch 40 needs to be performed in synchronization with the rising and falling switching of the signals of both oscillators 10 and 20, but since it is not directly related, the description is omitted.

When an external signal is used as the system clock, the switching signal becomes low level. As a result, the transmission gates 11 and 21 are cut off, the output of the NAND gate 60 is fixed at the high level, and the output of the AND 52 is fixed at the low level. Therefore, the external clock from the oscillator connection terminal 2 becomes the system clock through the OR gate 54.
Further, since the output of the inverter 70 becomes high level, the output of the latch 40 is output from the oscillator connection terminal 4 through the transmission gate 80.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.
This embodiment is different from the first embodiment in that the third oscillator circuit 3
0, its oscillator connection terminal 5, oscillator connection terminal and external clock input terminal 6, transmission gates 31, 81, latch 41, decoder 90, AND gate 53 are added, and OR gate 54 becomes a 3-input gate and AND The output of gate 53 is inserted. Decoder 90 outputs the outputs of latch 40 and latch 41.
AND51,52,5 by this decoding output
The point is that any one of the three is enabled selectively.

In this embodiment, a 2-bit latch is required to select the oscillation circuits 10 to 30, and the information can be output from the oscillator connection terminal / external clock input terminals 4 and 6, respectively.

〔The invention's effect〕

As described above, according to the present invention, a means for forcibly prohibiting internal clock switching in an integrated circuit that uses one of a plurality of oscillation circuits as a system clock according to an internal operating state, and a clock switching state as an external signal. By adding a means to output to, it is possible to perform a synchronous operation with another chip by the clock supplied from the outside without using the built-in oscillator circuit, and output the internal clock switching state to the outside. Therefore, it is possible to change the clock frequency supplied from the outside by using this.

[Brief description of drawings]

1 and 2 are circuit diagrams of the first and second embodiments of the present invention. 1,3,5 …… Resonator connection terminal, 2,4,6 …… Resonator connection terminal and external clock input terminal, 7 …… Clock terminal, 8 …… Switching terminal, 10,20,30 …… Oscillation circuit , 11,21,31,80,81 …… Transmission gate, 40,41 …… Latch, 51 ～ 53…
… AND gate, 54 …… OR gate, 60 …… NAND gate, 70
...... Inverter, 90 …… Decoder.

Claims (1)

[Claims] 1. A plurality of oscillation circuits, and a selection register for instructing which one of the oscillation outputs of these oscillation circuits is selected.
A switching signal for switching between an external clock and an internal clock regardless of the contents of the selection register in an integrated circuit having a first gate means for selecting one of the oscillation outputs as a system clock according to an instruction from the selection register. A second gate circuit for selecting an output signal of a first oscillation circuit of the oscillation circuits as a system clock in accordance with the above, and the contents of the selection register according to the switching signal outside the oscillation circuit other than the first oscillation circuit. An integrated circuit having a third gate circuit for outputting from a clock input terminal.