JPH08223567A - Synchronizing method for coding frequency and decoding one with each other - Google Patents

Abstract

PURPOSE: To obtain the method for synchronizing coding and decoding frequencies in which a frequency of a coder is synchronously with frequency of a decoder with small scale configuration. CONSTITUTION: A write clock generator 4 generates a write clock synchronizing with an input video signal. An A/D converter 3 converts the input video signal into a digital signal based on a write clock signal. A frame synchronizer 5 writes a digital signal in and reads the signal based on a processing clock synchronized with the transmission clock out of a clock generator 5. A high efficiency coder 7 converts the digital video signal into a coding signal based on the processing clock. A modulator 9 modulates the coding signal into a modulation wave based on the transmission clock and sends the modulated signal. A clock generator 13 generates a demodulation clock of the processing clock based on the transmission clock obtained through demodulation by a demodulator 11. A high efficiency decoder 14 decodes the demodulated coding signal based on a demodulation clock of the processing clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encoding / decoding frequency synchronization method, and more particularly to encoding when a coded signal obtained by highly efficient coding of a video signal is transmitted and decoded by a decoding device. The present invention relates to an encoding and decoding frequency synchronization method for generating a reference clock synchronized with a reference clock in a device.

[0002]

2. Description of the Related Art In order for a decoding device to receive and decode a coded video signal which has been encoded with high efficiency, a reference clock synchronized with a reference clock used for generating the coded video signal in the coding device. Need to decrypt based on.

Therefore, conventionally, for example, on the transmitting side, the video signal is digitally coded by the digital coding means using a sampling clock created based on the horizontal synchronizing signal of the video signal, and further code mark inversion ( CMI) coded and transmitted, and CMI on the receiving side
In a video signal transmission system in which a code is decoded and further decoded by a decoding means using a sampling clock synchronized with the sampling clock on the transmission side, in the transmission side, an offense is given to the CMI coding rule of the CMI coding unit, and on the reception side This CM
A frequency synchronization method is known in which a foul code of the I code is detected and a sampling clock is created based on the detected code (JP-A-2-274032).

[0004]

However, since the above-mentioned conventional method transmits the information about the frequency of the sampling clock of the encoding device as low-speed digital information called foul code, the transmitting side transmits the encoded data at low speed. A circuit for superimposing digital information and a circuit for extracting low-speed digital information on the receiving side are required, which causes a problem of large circuit scale.

The present invention has been made in view of the above points,
An object of the present invention is to provide an encoding and decoding frequency synchronization method capable of synchronizing the frequencies on the encoding device side and the decoding device side with a small-scale configuration.

[0006]

In order to achieve the above object, the present invention generates a write clock synchronized with an input video signal, converts the input video signal into a digital signal based on the write clock, and converts the digital signal into a digital signal. Writing to the first frame synchronizer, reading a digital video signal from the first frame synchronizer based on a processing clock synchronized with the transmission clock, converting the digital video signal into an encoded signal based on the processing clock, and converting the encoded signal based on the transmission clock The modulator modulates and transmits the modulated wave, receives the modulated wave, demodulates the demodulator, demodulates the demodulator to generate a demodulation clock of the processing clock, and demodulates the demodulator. The demodulated coded signal obtained in this way is decoded by the decoder based on the demodulation clock.

Further, according to the present invention, the digital signal decoded by the decoder is sent to the second frame synchronizer based on the demodulated clock of the processing clock generated in synchronization with the transmission clock obtained by demodulating by the demodulator. The digital signal written by the second frame synchronizer is read based on the write clock and the read clock having the same frequency as the write clock.

[0008]

According to the present invention, a processing clock for encoding an input video signal in an encoding device is synchronized with a transmission clock, the encoded signal is modulated based on the transmission clock and then transmitted, and the decoding device modulates the modulated wave. , A transmission clock is extracted, a demodulation clock of a processing clock that is phase-synchronized with the extracted transmission clock is generated, and a demodulation coded signal is decoded with this demodulation clock. It is possible to synchronize the encoding processing clock frequency and the decoding processing clock frequency with a relatively simple circuit.

Further, according to the present invention, since the decoded digital signal written in the second frame synchronizer is read based on the read clock having the same frequency as the write clock, it is demodulated and extracted from the transmitted modulated wave. It is possible to read by a stable read clock that is asynchronous with the transmitted transmission clock.

[0010]

Next, an embodiment of the present invention will be described. FIG. 1 shows a block diagram of an embodiment of the present invention. In the figure, the video signal output from the signal source 1 is supplied to the encoding device 2 to be encoded, converted into a modulated wave and transmitted.
This modulated wave is received and decoded by the decoding device 10 and converted into the original video signal.

The encoder 2 comprises an AD converter 3, a write clock generator 4, a frame synchronizer 5, a clock generator 6, a high efficiency encoder 7, a transmission buffer 8 and a clock generator 9. The decoding device 10 includes a demodulator 11, a reception buffer 12, a clock generator 13, a high efficiency decoder 14, a frame synchronizer 15, a read clock generator 16 and a DA converter 17.

Next, the operation of this embodiment will be described.
The video signal from the signal source 1 is supplied to the AD converter 2 and the write clock generator 3, respectively. The write clock generator 4 generates a write clock frequency synchronized with a horizontal synchronizing signal of an input video signal, a subcarrier, and the like.
This write clock frequency is, for example, CCIR601.
It is 13.5 MHz which complies with the standard. The AD converter 2 samples the input video signal with a write clock, converts it into a digital video signal, and outputs it to the frame synchronizer 5.

The clock generator 6 generates a processing clock synchronized with the transmission clock. Here, the transmission clock frequency is 6 MHz, and the processing clock is 13.5 MHz, which is the same frequency as the write clock. This clock generator 6 is, for example, as shown in the block diagram of FIG.
300 frequency divider 21, phase comparator 22, low-pass filter (L
PF) 23, voltage controlled oscillator (VCO) 24 and 1/6
It is composed of a phase-locked loop (PLL) circuit including a 75-frequency divider 25.

As a result, the transmission clock of 6 MHz becomes
The frequency is 20k after being divided by the 1/300 frequency divider 21.
After being set to Hz, it is supplied to the phase comparator 22 and
The phase is compared with 20 kHz from the 5 frequency divider 25. The phase error signal from the phase comparator 22 is applied as a control voltage to the VCO 24 through the LPF 23 to variably control the output oscillation frequency thereof.

The output oscillation frequency of the VCO 24 is 13.5M.
While being output to the outside as a processing clock, the frequency is divided by 1/675 by the 1/675 frequency divider 25 to a frequency of 20 kHz and then supplied to the phase comparator 22. In this way, the 13.5 MHz processing clock phase-locked with the 6 MHz transmission clock is extracted from the VCO 24.

Referring back to FIG. 1 again, the structure of the frame synchronizer 5 is well known, and the digital video signal from the AD converter 3 is supplied to the clock generator 4 in one of the two internal memories. From 13.5MHz
At the same time as writing one frame or one field based on the write clock of the above, the other memory writes the digital video signal for one frame or one field just written to the processing clock of 13.5 MHz from the clock generator 6. Based on this, reading is alternately repeated for each frame or field (that is, the memory on the writing side and the memory on the reading side are alternately switched).

Since the write clock from the write clock generator 4 and the processing clock from the clock generator 6 are asynchronous, a slight frequency difference may occur between the write clock and the processing clock. As described above, the frame synchronizer 5 can freely perform reading independently of the timing of the input digital video signal (asynchronous processing). Therefore, even if the write clock and the read clock (processing clock) are asynchronous, encoding processing, etc. There is no problem with.

The digital video signal read by the frame synchronizer 5 in synchronization with the processing clock is supplied to the high-efficiency encoder 7 and encoded in accordance with a predetermined high-efficiency encoding method. The high-efficiency encoder 7 obtains a prediction error signal by performing inter-frame or intra-frame prediction processing on an input digital video signal, for example, and performs a discrete cosine transform (DCT) on the prediction error signal. , The output obtained by performing the quantization is encoded and output through the buffer.

The encoded signal taken out from the high efficiency encoder 7 is written in the transmission buffer 8 based on the processing clock from the clock generator 6, then read out based on the transmission clock of 6 MHz, and further, The modulator 9 modulates the signal in a predetermined modulation method and converts it into a modulated wave in the transmission frequency band.

The above-mentioned modulated wave is transmitted through the transmission line to the decoding device 1.
It is supplied to the demodulator 11 in 0 to be demodulated into a coded signal and the transmission clock is demodulated. The demodulated transmission clock is supplied to the clock generator 13 and the reception buffer 12 to write the demodulated coded signal output from the demodulator 11.

The clock generator 13 has the same configuration as that of the clock generator 6 shown in FIG. 2, whereby the clock generator 13 is synchronized with the input transmission clock, and the output processing clock of the clock generator 6 of the encoder 2 is used. A processing clock having the same frequency as that of (13.5 MHz in this case) is generated. The demodulated coded signal written in the reception buffer 12 is read out based on the processing clock from the clock generator 13 and further decoded by the high-efficiency decoder 14.

The digital video signal decoded and taken out by the high-efficiency decoder 14 is supplied to the frame synchronizer 15 and written based on the processing clock from the clock generator 13. The frame synchronizer 15 has the same structure as the frame synchronizer 5, and like the frame synchronizer 5, writes a digital video signal at a processing clock of 13.5 MHz, and a stable clock 13 from a read clock generator 16 asynchronous with this.
Reading is performed based on the read clock of 5 MHz. DA
The converter 17 digital-analog converts the digital video signal from the frame synchronizer 15 into the original video signal and outputs it.

As described above, in this embodiment, the processing clock of the video signal is synchronized with the transmission clock by the relatively simple and small-scale clock generators 6 and 13 and the frame synchronizers 5 and 15. It is possible to synchronize the processing clock frequency of the decoding device 10 with a relatively small configuration.

Further, in the present embodiment, the transmission clock reproduced by the decoding device 10 usually contains jitter, and therefore if this is used as it is for reproduction of the sampling clock, the decoded video signal is disturbed in hue or the like, Since the synchronizer 15 extracts the video signal with a stable read clock from the read clock 16, the adverse effect of jitter can be prevented.

The present invention is not limited to the above-described embodiment, and for example, the read clock generator 16 can be synchronized with an external video reference signal (black burst or the like), and it can be used with a peripheral system. It is also easy to synchronize the video signals. Also, the coding is not limited to high efficiency coding.

[0026]

As described above, according to the present invention,
By demodulating the modulated wave, extracting the transmission clock, generating the demodulation clock of the processing clock that is phase-synchronized with the extracted transmission clock, and decoding the demodulation coded signal with this demodulation clock It is possible to synchronize the processing clock frequency for encoding and the processing clock frequency for decoding by a relatively simple circuit called a phase synchronization circuit.

According to the present invention, the decoded digital signal written in the second frame synchronizer is
By reading based on the read clock having the same frequency as the write clock, it is possible to read with a stable read clock that is asynchronous with the transmission clock demodulated from the transmitted modulated wave.
A video signal can be stably restored without being affected by jitter.

[Brief description of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a block diagram of an example of the clock generator of FIG.

[Explanation of symbols]

 1 Signal Source 2 Encoding Device 3 AD Converter 4 Write Clock Generator 5, 15 Frame Synchronizer 6, 13 Clock Generator 7 High Efficiency Encoder 8 Transmission Buffer 9 Modulator 10 Decoding Device 11 Demodulator 12 Reception Buffer 14 High efficiency decoder 16 Read clock generator 17 DA converter

Claims (2)

[Claims] 1. A write clock synchronized with an input video signal is generated, the input video signal is converted into a digital signal based on the write clock, the digital signal is written into a first frame synchronizer, and the digital clock is synchronized with a transmission clock. The digital signal is read from the first frame synchronizer based on the processed clock, converted into a coded signal based on the process clock, and the coded signal is modulated into a modulated wave by a modulator based on the transmission clock. Transmitted, the modulated wave is received, demodulated by a demodulator, demodulated by the demodulator to generate a demodulation clock of the processing clock based on the transmission clock, and the demodulator demodulates An encoding and decoding frequency synchronization method, characterized in that the demodulated coded signal is decoded by a decoder based on the demodulated clock. 2. A digital signal decoded by the decoder in a second frame synchronizer based on a demodulation clock of the processing clock generated in synchronization with the transmission clock obtained by demodulation by the demodulator. Write
2. The encoding and decoding frequency synchronization method according to claim 1, wherein the written digital signal is read by the second frame synchronizer based on a read clock having the same frequency as the write clock.