JPH08340238A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] [Object] An object of the present invention is to provide a semiconductor integrated circuit device including a delay circuit capable of reducing the power supply voltage dependency of the delay time. [Structure] An inverter 13 for receiving an input signal, an output signal line 11 connected to the output of the inverter 13, and a switch circuit 1 in which one end of a current path is connected to the output signal line 11.
7. A delay circuit 1 including a capacitor 15 having one electrode connected to the other end of the current path of the switch circuit 11, and a power supply voltage fluctuation detection circuit 9 for controlling the switch circuit 11.
Have and. When detecting the fluctuation of the power supply voltage, the detection circuit 9 turns on or off the switch circuit 11, connects the capacitor 15 to the output signal line 11, or outputs the output signal line 1.
The capacitor 15 is separated from 1, the capacitance of the output signal line 11 is changed, and the delay time of the delay circuit 1 is adjusted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a delay circuit for a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device, a delay circuit is often incorporated in order to adjust the timing of signals. A circuit generally called a delay circuit is a circuit that produces an output signal with respect to an input signal after a certain time. This "certain time" is called a delay time, and as a method for controlling this delay time, the following method has been conventionally used.

(1) The number of inverter stages is increased. (2) Combine the inverter and the capacitor. The method (1) utilizes the delay of the inverter itself, and the delay time can be lengthened by increasing the number of inverter stages.

The method (2) is the discharge characteristic of the capacitor,
Alternatively, the charging characteristic is used, and a longer delay time can be obtained by connecting a capacitor to the output wiring of the inverter as compared with the method (1).

FIG. 19 is a circuit diagram of a conventional delay circuit in which an inverter and a capacitor are combined. As shown in FIG. 19, the capacitor 102 is connected to the output wiring 101 of the inverter 100. Inverter 100
Is a CMOS type inverter, and the capacitor 102
Is an N-channel type MOS capacitor 103. The source and drain of the MOS capacitor 103 are connected to the low potential power supply VSS, and the gate thereof is connected to the wiring 101.

Next, the operation will be described. Input signal V
With IN at the VSS level, the MOS capacitor 103
Was fully charged. When the input signal VIN switches to the VCC level from this state, the inverter 1
An N-channel MOS transistor (not shown) in 00 is turned on to discharge the wiring 101. At this time, since the MOS capacitor 103 is charged, it takes time to discharge the entire wiring 101.

As described above, in the delay circuit shown in FIG.
To bring the potential of the wiring 101 to the VSS level, the wiring 10
It is possible to obtain a long time for discharging 1 and the MOS capacitor 103 respectively.

[0008]

However, as shown in FIG.
In the delay circuit shown in, the delay time depends on the power supply voltage VCC. FIG. 20 is a diagram showing the relationship between the delay time and the power supply voltage.

As shown in FIG. 20, the delay time becomes shorter as the power supply voltage VCC increases. In such a delay circuit having a strong power supply voltage dependency, if the power supply voltage VCC changes, the delay time changes, which may confuse the operation of the integrated circuit.

When designing an integrated circuit, first, a certain power supply voltage (designed power supply voltage) is determined, and a transistor, a standard circuit (for example, a logic circuit), a delay circuit and the like are combined. After that, the delay time required for the operation of the integrated circuit is determined in the delay circuit.

In an integrated circuit made by such a circuit design, if the operation is to be guaranteed with a wide range of power supply voltage VCC, the circuit design is difficult. Under such circumstances, it is desirable that the delay circuit has small power supply voltage dependency.

The present invention has been made in view of the above points, and an object thereof is to provide a semiconductor integrated circuit device including a delay circuit capable of reducing the power supply voltage dependency of the delay time. Another object is to provide a semiconductor integrated circuit device including a delay circuit whose delay time can be changed according to an operation mode.

[0013]

In order to achieve the above object, according to the present invention, a detection circuit for detecting a fluctuation of a power supply voltage and a capacitance circuit are provided, and in accordance with an output signal from the detection circuit, It is characterized in that the capacitance of the wiring is changed by connecting a capacitance circuit to the wiring.

In order to achieve the above-mentioned another object, according to the present invention, a mode circuit which defines an operation mode and a capacitance circuit are provided, and the capacitance circuit is provided in the wiring according to the output signal from the mode circuit. The feature is that the capacity of the wiring is changed by connecting.

[0015]

In the semiconductor integrated circuit device having the above-mentioned structure, depending on the output signal from the detection circuit or the mode circuit,
Since the capacitance circuit is connected to the wiring, the capacitance of the wiring becomes variable. If the capacitance of the wiring is variable, the delay amount of the signal flowing through this wiring is variable. If the above delay amount is increased or decreased according to the power supply voltage or the operation mode, the power supply voltage dependency of the delay time is reduced, or the delay time can be changed according to the operation mode. The circuit can be obtained.

[0016]

EXAMPLES The present invention will be described below with reference to examples. In this description, the same parts are denoted by the same reference numerals in all the drawings, and duplicated description will be avoided. 1A and 1B are diagrams showing a semiconductor integrated circuit device including a delay circuit according to a first embodiment of the present invention. FIG. 1A is a block diagram, FIG. 1B is a circuit diagram of a delay circuit, and FIG. FIG. 3 is a circuit diagram of a power supply voltage fluctuation detection circuit.

As shown in FIG. 1A, the delay circuit 1 has
It has an input unit 3, an output unit 5, and an input unit 7 for adjusting signals. The input signal VIN is input to the input unit 3, and the input signal V
The output unit 5 outputs the output signal VOUT obtained by delaying IN by a predetermined delay time. The adjustment signal VP output from the power supply voltage fluctuation detection circuit 9 is input to the input unit 7. The detection circuit 9 detects the fluctuation of the power supply voltage and outputs the adjustment signal VP when the fluctuation exceeds a certain level. The delay circuit 1 receives the adjustment signal VP and adjusts the delay time.

Next, the delay circuit 1 and the detection circuit 9
A specific circuit will be described. First, in the delay circuit 1 included in the integrated circuit device according to the first embodiment, as shown in FIG. 1B, an inverter 13 having an input terminal connected to the input unit 3 and an output terminal connected to the output wiring 11 is provided. And a switch circuit 17 for connecting the capacitor 15 to the wiring 11.

The source of the inverter 13 is a high potential power source V.
A P-channel MOSFET 21 connected to CC and a gate connected to the input section 3, a source connected to a low potential power supply VSS (eg ground), a drain connected to the drain of the MOSFET 21, and a gate connected to the gate of the MOSFET 21. And an N-channel MOSFET 23.

The capacitor 15 is an N-channel type M whose source and drain are connected to the low potential power supply VSS.
The OS capacitor 25. The switch circuit 17 includes a P-channel MOSFET 27 having a source connected to the gate of the MOS capacitor 25, a drain connected to the signal line 11, and a gate connected to the input unit 7. When the MOSFET 27 is on, the MOS capacitor 25 is connected to the signal line 1
Connected to 1. On the other hand, when the MOSFET 27 is off, the MOS capacitor 25 is disconnected from the signal line 11.

The detection circuit 9 of the integrated circuit device according to the first embodiment is connected in series between the high potential power supply VCC and the low potential power supply VSS, as shown in FIG. 1C. It includes a voltage circuit 31, an inverter 33 having an input terminal connected to the output terminal of the voltage dividing circuit 31, and an inverter 35 having an input terminal connected to the output terminal of the inverter 33. A control signal VP1 is obtained from the output terminal of the inverter 33,
The adjustment signal VP2 is obtained from the output terminal of the inverter 35. The adjustment signal VP1 is input to the gate of the MOSFET 27. The adjustment signal VP2 is a signal of the inverted level of the adjustment signal VP1, but is not used in the device according to the first embodiment.

The voltage dividing circuit 31 includes a resistor 41 having one end connected to the power supply VCC, and a resistor 43 having one end connected to the other end of the resistor 41 and the other end connected to the power supply VSS. A voltage division signal obtained by dividing the power supply voltage is obtained from the interconnection point of the resistors 41 and 43, and the voltage division signal is input to the input terminal of the inverter 33. The inverter 33 inverts its output level when the potential level of the divided signal exceeds the threshold value of the inverter 33. That is, the detection circuit 9 is a kind of comparator that compares the voltage division level of the voltage division circuit 31 with the threshold value that serves as a reference for fluctuation detection. This comparator is
Detects that the power supply voltage has changed.

Next, the operation of the apparatus according to the first embodiment will be described. FIG. 2 is a diagram showing the relationship between the delay time and the power supply voltage. The vertical axis of FIG. 2 is the delay time (nsec)
The horizontal axis represents the power supply voltage (V).

As shown in FIG. 2, the power supply voltage VCC is V
When CC ≦ P0, the detection signal VP1 is at the VCC level and the detection signal VP2 is at the VSS level. Here, the potential P0
Is a reference potential for adjusting the delay time.

On the other hand, when the power supply voltage VCC is P0 <VCC, contrary to the above range, the detection signal VP1 is V
The SS level and the detection signal VP2 become the VCC level. First, the operation when the power supply voltage VCC is VCC ≦ P0 will be described.

[VCC≤P0] Detection signal VP1 is VCC
Since it is at the level, the PMOS transistor 27 shown in FIG. 1B is turned off, and the NMOS capacitor 25 is separated from the signal line 11.

In this state, the potential of the signal line 11 is raised (VOUT is raised in this embodiment) and the potential of the signal line 11 is lowered (VOU in this embodiment).
In both cases, it is delayed by one stage of the inverter 13.

Next, the operation when the power supply voltage VCC is P0 <VCC will be described. Since the [P0 <VCC] detection signal VP1 is at the VSS level, the PMOS transistor 27 shown in FIG. 1B is turned on and the NMOS capacitor 25 is connected to the signal line 11.

In this state, the rise of the potential of the signal line 11 (in this embodiment, the rise of VOUT) is delayed by about one stage of the inverter 13, and the signal line 11 is delayed.
The fall of the potential of (in this embodiment, the fall of VOUT) is delayed by one stage of the inverter 13 and the discharge of the NMOS capacitor 25. Therefore, as shown in FIG. 2, it is possible to increase the delay time particularly when the potential of the signal line 11 falls (signal line 11: VCC → VSS).

Next, the operation when the power supply voltage VCC is P0 <VCC will be described in more detail. First, when the potential of the input signal VIN is at the VSS level, the PMOS transistor 21 of the inverter 13 is on and the NMOS transistor 23 is off. The signal line 11 is a PMOS
It is charged to the VCC level by the transistor 21,
The potential of the output signal VOUT is at the VCC level. At this time, the NMOS capacitor 25 is charged to the VCC level.

Next, the potential of the input signal VIN switches from the VSS level to the VCC level. Then, the PMOS transistor 21 of the inverter 13 is turned off and the NMOS transistor 23 is turned on. The signal line 11 is discharged by the NMOS transistor 23, and the potential of the signal line 11 decreases from the VCC level to the VSS level.
At this time, the NMOS capacitor 25 is discharged. Therefore, the time required for discharging the NMOS capacitor 25 is further added to the time required for the potential of the output signal VOUT to reach the VSS level.

Next, with the potential of the signal line 11 at the VSS level, the potential of the input signal VIN switches from the VCC level to the VSS level. Then inverter 1
The third PMOS transistor 21 is turned on and the NMOS transistor 23 is turned off. The signal line 11 is charged to the VCC level by the PMOS transistor 21, and the potential of the signal line 11 rises from the VSS level to the VCC level. At this time, since the substrate side electrode of the NMOS capacitor 25 is at the VSS level, charging to the VCC level is fast, and the delay due to the NMOS capacitor 25 is at a negligible level.

As described above, according to the device of the first embodiment, when the power supply voltage VCC becomes higher than the reference level P0, the switch circuit 17 causes the NMOS capacitor 25 to operate.
, Are automatically connected to the signal line 11. When the NMOS capacitor 25 is connected to the signal line 11, the delay time increases, and as shown in FIG. 2, the delay time that has decreased with the increase of the power supply voltage VCC is equal to or less than the reference level P0. It can be returned to a level almost equal to the delay time. Therefore, the dependency of the delay time on the power supply voltage, that is, the delay time becomes shorter as the power supply voltage VCC becomes higher, can be eliminated.

In the semiconductor integrated circuit device including such a delay circuit, it is possible to always operate normally even if the input power supply voltage VCC covers a wide range. Next, a semiconductor integrated circuit device including a delay circuit according to the second embodiment of the present invention will be described.

FIG. 3 is a circuit diagram of a semiconductor integrated circuit device including a delay circuit according to the second embodiment of the present invention. The device according to the second embodiment is similar to the device according to the first embodiment, and instead of the fall of the potential of the signal line 11, the rise of the potential of the signal line 11 is delayed by a larger amount. Can be applied.

As shown in FIG. 3, the device according to the second embodiment is different from the device according to the first embodiment in that the switch circuit 17 includes an NMOS transistor 28, and the capacitor 15 includes a PMOS capacitor 26. Is different. The PMOS capacitor 26 has its source and drain connected to the high potential power supply VCC. As the detection circuit 9, the one shown in FIG. 1C is used, and the adjustment signal VP2 is input to the gate of the NMOS transistor 28 of the switch circuit 17 instead of the adjustment signal VP1.

Next, the operation of the apparatus according to the second embodiment will be described. FIG. 4 is a diagram showing the relationship between the delay time and the power supply voltage. The vertical axis of FIG. 4 is the delay time (nsec),
The horizontal axis represents the power supply voltage (V).

First, the operation when the power supply voltage VCC is VCC≤P0 will be described. Since the [VCC ≦ P0] detection signal VP2 is at the VSS level, the NMOS transistor 28 shown in FIG. 3 is turned off and the PMOS capacitor 26 is separated from the signal line 11.

In this state, the potential of the signal line 11 is raised (VOUT is raised in this embodiment) and the potential of the signal line 11 is lowered (VOU in this embodiment).
In both cases, it is delayed by one stage of the inverter 13.

Next, the operation when the power supply voltage VCC is P0 <VCC will be described. Since the [P0 <VCC] detection signal VP2 is at the VCC level, the NMOS transistor 28 shown in FIG. 3 is turned on and the PMOS capacitor 26 is connected to the signal line 11.

In this state, the rise of the potential of the signal line 11 (in this embodiment, the rise of VOUT) is delayed by one stage of the inverter 13 and the discharge of the NMOS capacitor 25, so that the potential of the signal line 11 rises. The fall (in this embodiment, the fall of VOUT) is delayed by about one stage of the inverter 13. Therefore, as shown in FIG. 4, it is possible to increase the delay time particularly when the potential of the signal line 11 rises (signal line 11: VSS → VCC).

Next, the operation when the power supply voltage VCC is P0 <VCC will be described in more detail. First, when the potential of the input signal VIN is at the VCC level, the PMOS transistor 21 of the inverter 13 is off and the NMOS transistor 23 is on. The signal line 11 is an NMOS
It is charged to the VSS level by the transistor 23,
The potential of the output signal VOUT is at the VSS level. At this time, the PMOS capacitor 26 is charged to the VSS level.

Next, the potential of the input signal VIN switches from the VCC level to the VSS level. Then, the PMOS transistor 21 of the inverter 13 is turned on and the NMOS transistor 23 is turned off. The signal line 11 is charged by the PMOS transistor 21, and the potential of the signal line 11 rises from the VSS level to the VCC level.
At this time, the PMOS capacitor 26 is discharged. Therefore, the time required for discharging the PMOS capacitor 26 is further added to the time required for the potential of the output signal VOUT to reach the VCC level.

Next, with the potential of the signal line 11 at the VCC level, the potential of the input signal VIN switches from the VSS level to the VCC level. Then inverter 1
3, the PMOS transistor 21 is turned off, and the NMOS transistor 23 is turned on. The signal line 11 is discharged by the NMOS transistor 23, and the potential of the signal line 11 becomes
It decreases from the VCC level to the VSS level. At this time, the substrate side electrode of the PMOS capacitor 26 is at VCC
Since it is a level, it will charge to that VSS level quickly and the delay due to the PMOS capacitor 26 will be a negligible level.

Next explained is a semiconductor integrated circuit device including a delay circuit according to the third embodiment of the invention. Figure 5
FIG. 9 is a circuit diagram of a semiconductor integrated circuit device including a delay circuit according to a third embodiment of the present invention.

The device according to the third embodiment has a signal line 1
Both the fall and rise of the potential of 1 can be delayed. As shown in FIG. 5, the signal line 11 is connected to the PMOS transistor 2 shown in FIG.
7 and the NMOS capacitor 25, and the NM shown in FIG.
The OS transistor 28 and the PMOS capacitor 26 are connected to each other.

As the detection circuit 9, the one shown in FIG. 1C is used, and the adjustment signal VP1 is supplied to the first switch circuit 1.
7-1 is input to the gate of the PMOS transistor 27, and the adjustment signal VP2 is input to the gate of the NMOS transistor 28 of the second switch circuit 17-2.

Further, the circuit shown in FIG. 5 is connected to an inverter 13-2 having an input terminal connected to the signal line 11. The inverter 13-2 is an output stage that inverts and outputs the potential of the signal line 11. The inverter 13-2 is
It may be removed as in the first and second embodiments.

Next, the operation of the apparatus according to the third embodiment will be described. FIGS. 6A and 6B are diagrams showing the relationship between the delay time and the power supply voltage. FIG. 6 (a),
(B) Each vertical axis represents delay time (nsec), and horizontal axis represents power supply voltage (V).

First, the operation when the power supply voltage VCC is VCC≤P0 will be described. [VCC ≦ P0] Since the detection signal VP1 is at the VCC level and the detection signal VP2 is at the VSS level, P shown in FIG.
Both the MOS transistor 27 and the NMOS transistor 28 are turned off, and the NMOS capacitor 25 and the PMOS capacitor 26 are separated from the signal line 11, respectively.

In this state, the potential of the signal line 11 is raised and the potential of the signal line 11 is lowered.
The inverter 13-1 is delayed by one stage. Next, the operation when the power supply voltage VCC is P0 <VCC will be described.

[P0 <VCC] Detection signal VP1 is VSS
Since the level and the detection signal VP2 are at the VCC level,
PMOS transistor 27 and NMOS shown in FIG.
The transistors 28 are both turned on, and the NMOS capacitor 25 and the PMOS capacitor 26 are connected to the signal line 11, respectively.

In this state, in order to raise the potential of the signal line 11, one stage of the inverter 13-1 and the PMOS capacitor 2 are used.
6 is delayed, while the fall of the potential of the signal line 11 is delayed by one stage of the inverter 13-1 and the discharge of the NMOS capacitor 25. Therefore, as shown in FIG. 6A, the delay time when the potential of the signal line 11 is lowered (signal line 11: VCC → VSS), and as shown in FIG. The delay time when the potential is raised (signal line 11: VSS → VCC) can be increased respectively.

Next, the operation when the power supply voltage VCC is P0 <VCC will be described in more detail. First, when the potential of the input signal VIN is at the VSS level, the PMOS transistor 21-1 of the inverter 13-1 is turned on and the NMOS transistor 21-1 is turned on.
The transistor 23-1 is off. The signal line 11 is P
It is charged to the VCC level by the MOS transistor 21-1, and the potential of the signal line 11 is at the VCC level. At this time, the NMOS capacitor 25 is charged to the VCC level.

Next, the potential of the input signal VIN switches from the VSS level to the VCC level. Then, the PMOS transistor 21-1 of the inverter 13-1 is turned off and the NMO
The S transistor 23-1 turns on. The signal line 11 is NM
The signal line 1 is discharged by the OS transistor 23-1.
The potential of 1 drops from the VCC level to the VSS level. At this time, the NMOS capacitor 25 is discharged. Therefore, the time required for discharging the NMOS capacitor 25 is further added to the time required for the potential of the signal line 11 to reach the VSS level. At this time, since the substrate-side electrode of the PMOS capacitor 26 is at the VCC level,
Charge to the VSS level is fast, and the PMOS capacitor 26
The delay due to is at a negligible level.

Next, with the potential of the signal line 11 at the VSS level, the potential of the input signal VIN switches from the VCC level to the VSS level. Then inverter 1
The 3-1 PMOS transistor 21-1 is turned on and the NMOS transistor 23-1 is turned off. The signal line 11 is a PMOS
It is charged by the transistor 21-1, and the potential of the signal line 11 rises from the VSS level to the VCC level. At this time, the PMOS capacitor 26 is discharged. Therefore, the time required for discharging the PMOS capacitor 26 is further added to the time required for the potential of the output signal VOUT to reach the VCC level. At this time, since the substrate side electrode of the NMOS capacitor 25 is at the VSS level,
The charge to the VCC level is fast, and the NMOS capacitor 25
The delay due to is at a negligible level.

Next explained is a semiconductor integrated circuit device including a delay circuit according to the fourth embodiment of the invention. Figure 7
FIG. 9 is a circuit diagram of a delay circuit included in a semiconductor integrated circuit device according to a fourth embodiment of the present invention.

The device according to the fourth embodiment is intended to increase the delay time of the delay circuit 1.
In order to increase the delay time of the delay circuit 1, the fourth
In the device according to the embodiment, a plurality of delay stages including the inverter 13, the switch circuit 17, and the capacitor 15 are provided, and these delay stages are connected in series to configure the delay circuit 1.

As shown in FIG. 7, the first-stage inverter 13
The output of -1 is connected to the first signal line 11A. The first signal line 11A is turned on according to the adjustment signal VP2.
The first switch circuit 17-1 which is turned off is connected.
The first signal line 11A is connected to the input of the second stage inverter 13-2, and the output of this second stage inverter 13-2 is connected to the second signal line 11B. A second switch circuit 17-2, which is turned on / off according to the adjustment signal VP1, is connected to the second signal line 11B. The second signal line 11B is connected to the input of the last stage inverter 13-3. The final stage inverter 13-3 outputs the output signal VOU.
This is an output stage that outputs T, and may be removed as in the third embodiment.

As the detection circuit 9, the one shown in FIG. 1C is used, and the adjustment signal VP1 is inputted to the gate of the PMOS transistor 27 of the second switch circuit 17-2,
The control signal VP2 is supplied to the NMO of the first switch circuit 17-1.
Input to the gate of the S transistor 28.

Next, the operation of the apparatus according to the fourth embodiment will be described. FIG. 8 is a diagram showing the relationship between the delay time and the power supply voltage. The vertical axis of FIG. 8 is the delay time (nsec),
The horizontal axis represents the power supply voltage (V).

First, the operation when the power supply voltage VCC is VCC≤P0 will be described. [VCC ≦ P0] Since the adjustment signal VP1 is at the VCC level and the adjustment signal VP2 is at the VSS level, P shown in FIG.
Both the MOS transistor 27 and the NMOS transistor 28 are turned off, the NMOS capacitor 25 is isolated from the first signal line 11A, and the PMOS capacitor 26 is isolated from the second signal line 11B.

In this state, the rise and fall of the potential of the first signal line 11A is delayed by one stage of the first-stage inverter 13-1 and the rise and rise of the potential of the second signal line 11B. To lower the second stage inverter 13
-2 It takes only one step.

The delay time of the delay circuit 1 shown in FIG.
Output signal VO from the rise of the potential of CC input signal VIN
Both from the fall of UT and from the fall of the potential of the input signal VIN to the rise of the output signal VOUT,
Delay times of three stages of inverters 13-1 to 13-3 can be obtained.

Next, the operation when the power supply voltage VCC is P0 <VCC will be described. [P0 <VCC] Since the control signal VP1 is at the VSS level and the control signal VP2 is at the VCC level, P shown in FIG.
Both the MOS transistor 27 and the NMOS transistor 28 are turned on, the NMOS capacitor 25 is connected to the first signal line 11A, and the PMOS capacitor 26 is connected to the second signal line 11B.

In this state, the fall of the first signal line 11A is delayed by the first stage inverter 13-1 and the discharge of the NMOS capacitor 25, and the second signal line 1A is delayed.
To start up 1B, the second stage inverter 13-2 1st stage, P
There is a delay due to the discharge of the MOS capacitor 26. In addition, the rise of the first signal line 11A is delayed by only one stage of the first stage inverter 13-1, and the fall of the second signal line 11B is delayed by only one stage of the second stage inverter 13-2.

During the delay time of the delay circuit 1 shown in FIG. 7, when the power supply voltage VCC becomes equal to or higher than the potential P0 as shown in FIG. 8, the potential of the input signal VIN rises and the output signal V
Since the time required to discharge the NMOS capacitor 25 and the time required to discharge the PMOS capacitor 26 are added to the delay time of the three stages of the inverters 13-1 to 13-3 before the fall of OUT, the first to the first More time is obtained than with the device described by the third embodiment. On the other hand, a delay time of three stages of inverters 13-1 to 13-3 can be obtained from the fall of the potential of the input signal VIN to the rise of the output signal VOUT.

Next, the operation when the power supply voltage VCC is P0 <VCC will be described in more detail. First, when the potential of the input signal VIN is at the VSS level, the PMOS transistor 21-1 of the first stage inverter 13-1 is turned on and NM
The OS transistor 23-1 is off. The first signal line 11A is connected to VC by the PMOS transistor 21-1.
When charged to the C level, the potential of the first signal line 11A is V
It is CC level. At this time, the NMOS capacitor 25 is charged to the VCC level.

When the potential of the first signal line 11A is at the VCC level, the PMOS transistor 21-2 of the second stage inverter 13-2 is off and the NMOS transistor 23-2 is on. The second signal line 11B is charged to the VSS level by the NMOS transistor 23-2, and the potential of the second signal line 11B is at the VSS level. At this time, the PMOS capacitor 26 is charged to the VSS level.

Next, the potential of the input signal VIN switches from the VSS level to the VCC level. Then, the PMOS transistor 21-1 of the first-stage inverter 13-1 is turned off and N
The MOS transistor 23-1 turns on. First signal line 1
1A is discharged by the NMOS transistor 23-1, and the potential of the first signal line 11A changes from the VCC level to V
It decreases to the SS level. At this time, the NMOS capacitor 25 is discharged. For this purpose, the first signal line 11
In the time required for the potential of A to reach the VSS level, N
The time required for discharging the MOS capacitor 25 is further added.

When the potential of the first signal line 11A becomes VSS level, the PMOS transistor 21-2 of the second stage inverter 13-2 is turned on and the NMOS transistor 23-2 is turned off. The second signal line 11B is connected to the PMOS transistor 2
By 1-2, it is charged to the VCC level, and the potential of the second signal line 11B rises from the VSS level to the VCC level. At this time, the PMOS capacitor 26 is discharged. Therefore, the potential of the second signal line 11B becomes VCC.
The time required to discharge the PMOS capacitor 26 is further added to the time required to reach the level.

When the potential of the second signal line 11B becomes the VCC level, the PMOS transistor 21-3 of the final stage inverter 13-3 is turned off, the NMOS transistor 23-3 is turned on, and the output signal VOUT is changed from the VCC level to the VSS level. Lower to a level.

Next, the potential of the second signal line 11B becomes VCC.
When the potential of the input signal VIN is VC
Switch from C level to VSS level. Then, the PMOS transistor 21-1 of the first stage inverter 13-1 is turned on and the NMOS transistor 23-1 is turned off. The first signal line 11A is connected by the PMOS transistor 21-1.
It is charged to the VCC level, and the potential of the first signal line 11A rises from the VSS level to the VCC level.
At this time, in the NMOS capacitor 25, the substrate side electrode is V
Due to the SS level, charging to the VCC level is fast.

When the potential of the first signal line 11A reaches the VCC level, the PMOS transistor 21-2 of the second stage inverter 13-2 is turned off and the NMOS transistor 23-2 is turned on. The second signal line 11B is connected to the NMOS transistor 2
3-2, the second signal line 11B is discharged and the potential of the second signal line 11B decreases from the VCC level to the VSS level.
At this time, the substrate side electrode of the PMOS capacitor 26 is V
Due to the CC level, charging to the VSS level is fast.

When the potential of the second signal line 11B becomes VSS level, the PMOS transistor 21-3 of the final stage inverter 13-3 is turned on and the NMOS transistor 23-3 is turned off, and the output signal VOUT is changed from VSS level to VCC. Raise to a level.

Next explained is a semiconductor integrated circuit device including a delay circuit according to the fifth embodiment of the invention. Figure 9
Is a diagram showing a semiconductor integrated circuit device including a delay circuit according to a fifth embodiment of the present invention, FIG.
(B) is a circuit diagram of the delay circuit, and (c) is a circuit diagram of the power supply voltage fluctuation detection circuit.

The device according to the fifth embodiment is intended to increase the delay time of the delay circuit 1 in several stages. In order to increase the delay time of the delay circuit 1 in several stages, in the device according to the fifth embodiment, a capacitance including a switch circuit 17 that is turned on / off according to the adjustment signal VP and a capacitor 15 is included. A plurality of circuits are provided and these capacitance circuits are connected to one signal line 11. Then, the number of capacitors 15 connected to one signal line 11 is gradually increased by the switch circuit 17. Further, in order to increase the number of capacitors 15 connected to one signal line 11 in a stepwise manner, the detection circuit 9 increases or decreases the number of outputs of the adjustment signal VP according to the rise of the power supply voltage. .

First, the delay circuit 1 will be described. Figure 9
As shown in (b), the output of the inverter 13-1 is connected to the signal line 11. The signal line 11 has a first switch circuit 17-1 which is turned on / off according to the first adjustment signal VP3 and a second switch circuit 17-2 which is turned on / off according to the second adjustment signal VP4. And are connected. First
Switch circuit 17-1 includes an NMOS transistor 28, and similarly, the second switch circuit 17-2 includes an NMOS transistor 28. The first capacitor 15-1 is a PMO
An S capacitor 26, and likewise a second capacitor 1
5-2 includes a PMOS capacitor 26.

Next, the detection circuit 9 will be described. Figure 9
As shown in (c), the detection circuit 9 uses the high potential power supply VCC.
Voltage dividing circuit 31 including resistors 41, 42 and 43 connected in series between the low voltage source VSS and the low potential power source VSS, and the resistor 41.
33-1 in which an input terminal is connected to the interconnection point of the resistor 42 and the resistor 42, an inverter 33-2 in which an input terminal is connected to the interconnection point of the resistor 42 and the resistor 43, and an inverter 33
Inverter 35-1 with input terminal connected to output terminal of -1
And an inverter 35-2 having an input terminal connected to the output terminal of the inverter 33-2. The first adjustment signal VP3 is
The second adjustment signal VP4 is obtained from the output terminal of the inverter 35-1, and the second adjustment signal VP4 is obtained from the output terminal of the inverter 35-2.

FIG. 10 is a diagram showing the relationship between the delay time and the power supply voltage. The vertical axis of FIG. 10 indicates the delay time (nsec)
The horizontal axis represents the power supply voltage (V). As shown in FIG. 10, when the power supply voltage VCC is VCC ≦ P1, both the adjustment signals VP3 and VP4 are at the VSS level. When the power supply voltage VCC rises and becomes in the range of P1 <VCC ≦ P2,
Only the adjustment signal VP3 becomes the VCC level. Power supply voltage V
When CC further rises to the range of P2 <VCC,
Both the adjustment signals VP3 and VP4 are at the VCC level.

First, the operation when the power supply voltage VCC is VCC≤P1 will be described. [VCC ≦ P1] Both the control signals VP3 and VP4 are VS
Since it is at the S level, the NMOS transistor 28 of the first switch circuit 17-1 shown in FIG.
The NMOS transistor 28 of the switch circuit 17-2 is turned off, and the PMOS capacitor 26 of the first capacitor 15-1 and the PMOS capacitor 26 of the second capacitor 15-2 are separated from the signal line 11.

In this state, both the fall and rise of the signal line 11 are delayed by one stage of the inverter 13-1. The delay time of the delay circuit 1 shown in FIG.
Output signal VO from the rise of the potential of CC input signal VIN
Both from the fall of UT and from the fall of the potential of the input signal VIN to the rise of the output signal VOUT,
A delay time of two stages of the inverter 13-1 and the inverter 13-2 can be obtained.

Next, the power supply voltage VCC is P1 <VCC ≦
The operation at P2 will be described. [P1 <VCC ≦ P2] Since the adjustment signal VP3 is at the VCC level and the adjustment signal VP4 is at the VSS level, FIG.
Only the NMOS transistor 28 of the first switch circuit 17-1 shown in (b) is turned on to turn on the first capacitor 15-1.
Only the NMOS capacitor 26 of is connected to the signal line 11.

In this state, when the signal line 11 is lowered,
Inverter 13-1 is delayed by only one stage, and signal line 11
To start up, one inverter 13-1 and one NMO
There is a delay due to the discharge of the S capacitor 26.

In the delay time of the delay circuit 1 shown in FIG. 9B, as shown in FIG. 10, from the fall of the potential of the VCC input signal VIN to the fall of the output signal VOUT.
In the delay time of the two stages of the inverters 13-1 and 13-2, one N
The time required for discharging the MOS capacitor 26 is added. On the other hand, from the rise of the potential of the input signal VIN to the rise of the output signal VOUT, the inverters 13-1, 1
3-2 Two delay times can be obtained.

Next, the power supply voltage VCC is P1 <VCC ≦
The operation at P2 will be described in more detail. First, when the potential of the input signal VIN is at the VCC level, the PMOS transistor 21-1 of the inverter 13-1 is turned off,
The NMOS transistor 23-1 is on. Signal line 1
The potential of 1 is V by the NMOS transistor 23-1.
It is SS level. At this time, the PMOS capacitor 26 of the first capacitor 15-1 is charged to the VSS level.

Next, the potential of the input signal VIN switches from the VCC level to the VSS level. Then, the PMOS transistor 21-1 of the inverter 13-1 turns on and the NMO
The S transistor 23-1 is turned off. The potential of the signal line 11 is raised from the VSS level to the VCC level by the PMOS transistor 21-1. At this time, the PMOS capacitor 26 of the first capacitor 15-1 is discharged.
Therefore, the time required for discharging one PMOS capacitor 26 is further added to the time required for the potential of the signal line 11 to reach the VCC level.

Next, with the potential of the signal line 11 at the VCC level, the potential of the input signal VIN switches from the VSS level to the VCC level. Then inverter 1
The 3-1 PMOS transistor 21-1 is turned off and the NMOS transistor 23-1 is turned on. The signal line 11 is an NMOS
Transistor 23-1 changes from VCC level to VSS
Can be lowered to a level. At this time, since the substrate-side electrode of the PMOS capacitor 26 is at the VCC level,
Charging to VSS level is fast.

Next, the operation when the power supply voltage VCC is P2 <VCC will be described. [P2 <VCC] Control signals VP3 and VP4 are both VC
Since it is at the C level, the NMOS transistor 28 of the second switch circuit 17-2 shown in FIG. 9B is turned on, and the NMOS capacitor 26 of the second capacitor 15-2 is turned on.
Is further connected to the signal line 11.

In this state, when the signal line 11 is lowered,
Inverter 13-1 is delayed by only one stage, and signal line 11
Inverter 13-1 one stage and two NMO to start up
There is a delay due to the discharge of the S capacitor 26.

In the delay time of the delay circuit 1 shown in FIG. 9B, as shown in FIG. 10, from the fall of the potential of the VCC input signal VIN to the fall of the output signal VOUT.
Inverters 13-1, 13-2 have two N delay times
The time required for discharging the MOS capacitor 26 is added. On the other hand, from the rise of the potential of the input signal VIN to the rise of the output signal VOUT, the inverters 13-1, 1
3-2 Two-stage delay time can be obtained.

Next, the operation when the power supply voltage VCC is P2 <VCC will be described in more detail. First, when the potential of the input signal VIN is at the VCC level, the PMOS transistor 21-1 of the inverter 13-1 is turned off and the NMOS
The transistor 23-1 is on. The potential of the signal line 11 is at the VSS level by the NMOS transistor 23-1. At this time, the PMOS capacitor 26 of the first capacitor 15-1 and the second capacitor 15
Both -2 PMOS capacitors 26 are charged to the VSS level.

Next, the potential of the input signal VIN switches from the VCC level to the VSS level. Then, the PMOS transistor 21-1 of the inverter 13-1 turns on and the NMO
The S transistor 23-1 is turned off. The potential of the signal line 11 is raised from the VSS level to the VCC level by the PMOS transistor 21-1. At this time, the PMOS capacitor 26 of the first capacitor 15-1 and the second capacitor
The PMOS capacitor 26 of the capacitor 15-2 is discharged. Therefore, the time required for discharging the two PMOS capacitors 26 is further added to the time required for the potential of the signal line 11 to reach the VCC level.

Next, with the potential of the signal line 11 at the VCC level, the potential of the input signal VIN switches from the VSS level to the VCC level. Then inverter 1
The 3-1 PMOS transistor 21-1 is turned off and the NMOS transistor 23-1 is turned on. The signal line 11 is an NMOS
Transistor 23-1 changes from VCC level to VSS
Can be lowered to a level. At this time, two PMOS
Each of the capacitors 26 is charged to the VSS level quickly because the substrate side electrode is at the VCC level.

As described above, according to the device of the fifth embodiment, the power supply voltage VCC is first set to the first reference level P1.
When it exceeds, one NMOS capacitor is automatically connected to the signal line 11 to increase the delay time. Further, when the power supply voltage VCC exceeds the first reference level P1 and further exceeds the second reference level P2, another NMOS is provided.
A capacitor is automatically connected to the signal line 11 to further increase the delay time. Therefore, the delay time of the delay circuit 1 is gradually increased as the power supply voltage VCC rises, and the delay time can be adjusted more accurately, for example.

Next explained is a semiconductor integrated circuit device including a delay circuit according to the sixth embodiment of the invention. FIG.
1 is a circuit diagram of a power supply voltage fluctuation detection circuit included in a semiconductor integrated circuit device according to a sixth embodiment of the present invention.

The device according to the sixth embodiment is intended to adjust the delay time of the delay circuit 1 in an analog manner. In order to adjust the delay time of the delay circuit 1 in an analog manner, in the device according to the sixth embodiment, the detection circuit 9
The voltage dividing point of the voltage dividing circuit 31 included in is directly connected to the switch circuit 17.

The voltage dividing circuit 31 shown in FIG. 11 has a configuration shown in FIG.
It has the same shape as that shown in. From the first voltage dividing point, that is, the interconnection point between the resistors 41 and 42, the first adjustment signal VP5 is obtained, and from the second voltage dividing point, that is, the interconnection point between the resistors 42 and 43. Results in a second adjustment signal VP6.

The detection circuit 9 shown in FIG. 11 is connected to the delay circuit 1 shown in FIG. 9B, and the first adjustment signal VP5 is applied to the gate of the switch circuit 17-1 shown in FIG. 9B, for example. Then, the second adjustment signal VP6 is input to the gate of the switch circuit 17-2 shown in FIG. 9B, for example.

In this way, in the device according to the fifth embodiment, when the power supply voltage VCC gradually increases, first, the potential of the adjustment signal VP5 becomes NM of the switch circuit 17-1.
The threshold of OS28 is exceeded. Switch circuit 17-1 N
The MOS 28 functions as a variable resistor whose resistance value decreases as the potential of the adjustment signal VP5 rises, and the power supply voltage VCC
The capacitance added to the signal line 11 is increased in accordance with the rise of the. When the power supply voltage VCC further rises, the potential of the control signal VP6 changes to the NMOS 28 of the switch circuit 17-2.
Exceeds the threshold of. NMOS2 of switch circuit 17-2
Similarly, 8 also functions as a variable resistor whose resistance value decreases as the potential of the adjustment signal VP6 rises.
As CC further increases, the capacity added to the signal line 11 is further increased.

As described above, according to the device of the sixth embodiment, the delay time of the delay circuit 1 can be adjusted in an analog manner, and the device of the fifth embodiment is different from that of the device of the fifth embodiment. Similarly, for example, the delay time can be adjusted more precisely.

The voltage dividing circuit 31 of the apparatus according to the sixth embodiment may be the voltage dividing circuit 31 shown in FIG. 1 (c). In this case, for example, when the delay circuit 1 shown in FIG. 3 is connected, the device according to the second embodiment can be configured to switch the delay time digitally from the delay time analog. .

Next explained is an apparatus according to the seventh embodiment of the invention. FIG. 12 is a block diagram of a semiconductor integrated circuit device including a delay circuit according to the seventh embodiment of the present invention.

The device according to the seventh embodiment is intended to switch the delay time of the delay circuit 1 according to the operation mode of the integrated circuit. In order to switch the delay time of the delay circuit 1 according to the operation mode of the integrated circuit, in the device according to the seventh embodiment, the switch circuit 17 and the capacitor 15 described in the first to sixth embodiments are provided. A delay circuit 1 having a capacitance circuit including the delay circuit 1 is used, and the delay time of the delay circuit 1 is switched by a control signal from the mode switching circuit 10.

As shown in FIG. 12, the switching circuit 10
Outputs, as a control signal, a mode signal VM that defines the operation mode of the integrated circuit (the first mode in this embodiment
Output the mode signal VM1 and the second mode signal VM1) and the mode signal VM to the delay circuit 1. The mode signal VM supplied to the delay circuit 1 may be a signal only for switching the delay time of the delay circuit 1, and
In order to define the overall operation mode of the integrated circuit, for example, an output control circuit for controlling the output, a signal for defining the operation of other circuit parts such as an output circuit controlled by this output control circuit It may be.

Next, the delay circuit 1 of the device according to the seventh embodiment will be described. FIG. 13 is a circuit diagram of the delay circuit 1 of the device according to the seventh embodiment. As shown in FIG.
The circuit of the delay circuit 1 is very similar to the configuration of the delay circuit 1 shown in FIG. 7 in that a plurality of delay stages including an inverter 13, a switch circuit 17, and a capacitor 15 are provided. The difference is that the second switch circuit 17-2 connected to the second signal line 11B is
8 is included, and the second capacitor 15-2 connected to the second switch circuit 17-2 includes an NMOS capacitor 25. N of the first switch circuit 17-1
The first mode signal VM1 is input to the gate of the MOS transistor 28, and the NMO of the second switch circuit 17-2 is input.
The gate of the S transistor 28 has a second mode signal VM
2 is input.

Next, the operation of the apparatus according to the seventh embodiment will be described. 14 is an operation waveform diagram of the delay circuit 1 shown in FIG. 13, (a) is an operation waveform diagram when VM1 = VSS, VM2 = VSS, and (b) is a VM1 = VCC, VM2 = VSS diagram. Operation waveform diagram of (1), (c) is the operation waveform diagram when VM1 = VSS, VM2 = VCC,
(D) is an operation waveform diagram when VM1 = VCC and VM2 = VCC.

First, the operation when both the first mode signal VM1 and the second mode signal VM2 are at the VSS level will be described. [VM1 = VSS, VM2 = VSS] Since both the first mode signal VM1 and the second mode signal VM2 are at the VSS level, the NMOS transistor 28 of the first switch circuit 17-1 and the second switch circuit 17-2 N
The MOS transistors 28 are turned off.

In this state, as shown in FIG. 14A, the first-stage inverter 1
From the fall of the output signal A and the fall of the input signal VIN of 3-1 to the rise of the output signal A, only one stage of the first stage inverter 13-1 is delayed.

Similarly, from the fall of the output signal A to the second
From the rise of the output signal B of the stage inverter 13-2 and the rise of the output signal A, the fall of the output signal B is delayed by only one stage of the second stage inverter 13-2.

Similarly, from the rising of the output signal B to the third
Both the fall of the output signal VOUT and the rise of the output signal VOUT of the stage inverter 13-3 are delayed by only one stage of the third stage inverter 13-3.

Therefore, the inverter 13 has both the delay time τ1 from the rise of the input signal VIN to the fall of the output signal VOUT and the delay time τ2 from the fall of the input signal VIN to the rise of the output signal VOUT.
Delays of -1 to 13-3 are obtained.

Next, the operation when the first mode signal VM1 is at the VCC level and the second mode signal VM2 is at the VSS level will be described. [VM1 = VCC, VM2 = VSS] Since the first mode signal VM1 is at the VCC level, the NMOS transistor 28 of the first switch circuit 17-1 is turned on, and the first capacitor 15-1 becomes the first Signal line 11A.

In this state, as shown in FIG. 14B, since the input signal VIN rises, the first-stage inverter 1
To the fall of the output signal A of 3-1 is added the delay due to the one stage of the inverter 13-1 and the delay due to the discharge of the NMOS capacitor 25 of the first capacitor 15-1. On the other hand, from the fall of the input signal VIN to the rise of the output signal A, only one stage of the inverter 13-1 is delayed.

In addition, from the fall of the output signal A to the rise of the output signal B of the second stage inverter 13-2, and from the rise of the output signal A to the fall of the output signal B, the second The stage inverter 13-2 is delayed by only one stage.

In addition, from the rise of the output signal B to the fall of the output signal VOUT of the third stage inverter 13-3, and from the fall of the output signal B to the rise of the output signal VOUT, the third The stage inverter 13-3 is delayed by only one stage.

Therefore, in the delay time τ1, the inverter 1
A delay obtained by discharging one NMOS capacitor 25 is added to the delay caused by the three stages 3-1 to 13-3. Further, only the delay due to the three stages of the inverters 13-1 to 13-3 can be obtained in the delay time τ2.

Next, the operation when the first mode signal VM1 is at the VSS level and the second mode signal VM2 is at the VCC level will be described. [VM1 = VSS, VM2 = VCC] Since the second mode signal VM2 is at the VCC level, the NMOS transistor 28 of the second switch circuit 17-2 is turned on and the second capacitor 15-2 is changed to the second capacitor 15-2. Signal line 11B.

In this state, as shown in FIG. 14 (c), the first-stage inverter 1 is operated after the input signal VIN rises.
From the fall of the output signal A and the fall of the input signal VIN of 3-1 to the rise of the output signal A, only one stage of the first stage inverter 13-1 is delayed.

Further, only one stage of the inverter 13-2 is delayed from the fall of the output signal A to the rise of the output signal B of the second stage inverter 13-2. On the other hand, from the rising of the output signal A to the falling of the output signal B, the inverter 1
3-2 NM of the second capacitor 15-2 due to the delay due to one stage
A delay due to the discharge of the OS capacitor 25 is added.

Further, from the rise of the output signal B to the fall of the output signal VOUT of the third stage inverter 13-3, and from the fall of the output signal B to the rise of the output signal VOUT, the third The stage inverter 13-3 is delayed by only one stage.

Therefore, in the delay time τ1, the inverter 1
Only the delay due to the three stages 3-1 to 13-3 is obtained, and the delay time τ2 is the delay due to the discharge of one NMOS capacitor 25 in addition to the delay due to the three stages of the inverters 13-1 to 13-3. Things are obtained.

Next, the operation when both the first mode signal VM1 and the second mode signal VM2 are at the VCC level will be described. [VM1 = VCC, VM2 = VCC] Both the first mode signal VM1 and the second mode signal VM2 are VCC
Because of the level, the NMO of the first capacitor 15-1
The S transistor 25 is connected to the first signal line 11A,
The NMOS transistor 25 of the second capacitor 15-2 is connected to the second signal line 11B.

In this state, as shown in FIG. 14 (d), the first-stage inverter 1 is started from the rising of the input signal VIN.
To the fall of the output signal A of 3-1 is added the delay due to the one stage of the inverter 13-1 and the delay due to the discharge of the NMOS capacitor 25 of the first capacitor 15-1. On the other hand, from the fall of the input signal VIN to the rise of the output signal A, only one stage of the inverter 13-1 is delayed.

Also, there is a delay of only one stage of the inverter 13-2 from the fall of the output signal A to the rise of the output signal B of the second stage inverter 13-2. On the other hand, from the rising of the output signal A to the falling of the output signal B, the inverter 1
3-2 NM of the second capacitor 15-2 due to the delay due to one stage
A delay due to the discharge of the OS capacitor 25 is added.

In addition, from the rise of the output signal B to the fall of the output signal VOUT of the third stage inverter 13-3, and from the fall of the output signal B to the rise of the output signal VOUT, the third The stage inverter 13-3 is delayed by only one stage.

Therefore, both the delay time τ1 and the delay time τ2 can be obtained by adding the delay due to the discharge of one NMOS capacitor 25 to the delay due to the three stages of the inverters 13-1 to 13-3.

Next, the delay circuit 1 of the device according to the eighth embodiment will be described. FIG. 15 is a circuit diagram of the delay circuit 1 of the device according to the eighth embodiment. The device according to the eighth embodiment is similar to the device according to the seventh embodiment, and instead of the fall of the signal lines 11A and 11B, the rise of the signal lines 11A and 11b is performed. ,
It can be delayed more.

As shown in FIG. 15, the device according to the eighth embodiment is the same as the device according to the seventh embodiment except that the first capacitor 15-1 includes the PMOS capacitor 26 and the second capacitor. The difference is that 15-2 includes a PMOS capacitor 26.

Next, the operation of the apparatus according to the eighth embodiment will be described. FIG. 16 is an operation waveform diagram of the delay circuit 1 shown in FIG. 15, (a) is an operation waveform diagram when VM1 = VSS, VM2 = VSS, and (b) is a VM1 = VCC, VM2 = VSS diagram. Operation waveform diagram of (1), (c) is the operation waveform diagram when VM1 = VSS, VM2 = VCC,
(D) is an operation waveform diagram when VM1 = VCC and VM2 = VCC.

First, the operation when both the first mode signal VM1 and the second mode signal VM2 are at the VSS level will be described. [VM1 = VSS, VM2 = VSS] Since both the first mode signal VM1 and the second mode signal VM2 are at the VSS level, the NMOS transistor 28 of the first switch circuit 17-1 and the second switch circuit 17-2 N
The MOS transistors 28 are turned off.

Therefore, as shown in FIG.
Similar to the device according to the seventh embodiment, the delay time τ from the rise of the input signal VIN to the fall of the output signal VOUT
1 and output signal VO from the fall of input signal VIN
The delay due to the three stages of the inverters 13-1 to 13-3 can be obtained in any of the delay times τ2 until the UT starts up.

Next, the operation when the first mode signal VM1 is at the VCC level and the second mode signal VM2 is at the VSS level will be described. [VM1 = VCC, VM2 = VSS] Since the first mode signal VM1 is at the VCC level, the NMOS transistor 28 of the first switch circuit 17-1 is turned on, and the first capacitor 15-1 becomes the first Signal line 11A.

In this state, as shown in FIG. 16B, in particular, the output signal A is changed from the fall of the input signal VIN.
In addition to the delay due to the one stage of the inverter 13-1, the delay due to the discharge of the PMOS capacitor 26 of the first capacitor 15-1 is added to the rise of the voltage.

Therefore, in the delay time τ1, the inverter 1
Only the delay due to three stages from 3-1 to 13-3 is obtained, and the delay time τ
2 has a delay due to three stages of inverters 13-1 to 13-3,
One obtained by adding a delay due to discharge of one PMOS capacitor 26 is obtained.

Next, the operation when the first mode signal VM1 is at the VSS level and the second mode signal VM2 is at the VCC level will be described. [VM1 = VSS, VM2 = VCC] Since the second mode signal VM2 is at the VCC level, the NMOS transistor 28 of the second switch circuit 17-2 is turned on and the second capacitor 15-2 is changed to the second capacitor 15-2. Signal line 11B.

In this state, as shown in FIG. 14C, in particular, from the fall of the output signal A to the rise of the output signal B, to the delay by one stage of the inverter 13-2, to the second capacitor 15-. A delay due to the discharge of the second PMOS capacitor 26 is added.

Therefore, the inverter 1 has the delay time τ1.
The delay due to the discharge of one PMOS capacitor 26 is added to the delay due to the three stages of 3-1 to 13-3, and the delay time τ2 is the delay due to the three stages of the inverters 13-1 to 13-3. Only get.

Next, the operation when both the first mode signal VM1 and the second mode signal VM2 are at the VCC level will be described. [VM1 = VCC, VM2 = VCC] Both the first mode signal VM1 and the second mode signal VM2 are VCC
Because of the level, the NMO of the first capacitor 15-1
The S transistor 25 is connected to the first signal line 11A,
The NMOS transistor 25 of the second capacitor 15-2 is connected to the second signal line 11B.

In this state, as shown in FIG. 14D, in particular, the output signal A is changed from the fall of the input signal VIN.
In addition to the delay due to the one stage of the inverter 13-1, the delay due to the discharge of the PMOS capacitor 26 of the first capacitor 15-1 is added to the rise of the voltage.

Further, from the fall of the output signal A to the rise of the output signal B, the delay due to one stage of the inverter 13-2, the PMOS capacitor 26 of the second capacitor 15-2.
The delay due to the discharge of is added.

Therefore, both the delay time τ1 and the delay time τ2 can be obtained by adding the delay due to the discharge of one NMOS capacitor 26 to the delay due to the three stages of the inverters 13-1 to 13-3.

As described above, the device according to the eighth embodiment operates similarly to the device according to the seventh embodiment, but the discharge characteristic of the NMOS capacitor and the PMO are included in the integrated circuit.
The optimum one should be created in consideration of the discharge characteristics of the S capacitor and the circuit logic.

Since a huge number of circuits are integrated in the integrated circuit, the optimum one is selected from the device according to the seventh embodiment and the device according to the eighth embodiment for each of these circuits. Alternatively, it may be properly used for each circuit.

Next, the delay circuit 1 of the device according to the ninth embodiment will be described. FIG. 17 is a circuit diagram of the delay circuit 1 of the device according to the ninth embodiment. In the device according to the ninth embodiment, the delay time τ1 and the delay time τ2 of the device according to the seventh embodiment or the eighth embodiment are both set at the same time.
It is going to be bigger. In order to increase the delay time, in the device according to the ninth embodiment, as shown in FIG.
As shown in FIG. 7, in addition to the circuit shown in FIG. 15, the third capacitor 15-3 is connected to the first signal line 11A via the third switch circuit 17-3, and the fourth capacitor 15- Four
Through the fourth switch circuit 17-4 to the second signal line 11
Connect to B. Then, the third capacitor 15-3 has an NM
The OS capacitor 25 is provided, and the NMOS capacitor 25 is provided on the fourth capacitor 15-4. Further, the third switch circuit 17-3 is controlled by the first mode signal VM1,
The switch circuit 17-4 is controlled by the second mode signal VM2.

With such a circuit, the switch circuit 1
When 7-1 and 17-3 are turned on, a delay due to discharge of the MOS capacitor can be added to both the rise and fall of the output signal A, and similarly, the switch circuit 17-
When 2 and 17-4 are turned on, a delay due to discharge of the MOS capacitor can be added to both the rise and fall of the output signal B.

Next, the operation of the apparatus according to the ninth embodiment will be described. 18 is an operation waveform diagram of the delay circuit 1 shown in FIG. 17, (a) is an operation waveform diagram when VM1 = VSS, VM2 = VSS, and (b) is a VM1 = VCC, VM2 = VSS diagram. Operation waveform diagram of (1), (c) is the operation waveform diagram when VM1 = VSS, VM2 = VCC,
(D) is an operation waveform diagram when VM1 = VCC and VM2 = VCC.

First, the operation when both the first mode signal VM1 and the second mode signal VM2 are at the VSS level will be described. [VM1 = VSS, VM2 = VSS] When both the first mode signal VM1 and the second mode signal VM2 are at the VSS level, the NMOS transistor 28 of the first switch circuit 17-1 to the fourth switch circuit 17-4 Respectively,
Turn off.

Therefore, as shown in FIG.
Similar to the devices according to the seventh and eighth embodiments, the input signal VIN
In each of the delay time τ1 from the rise of the output signal VOUT to the fall of the output signal VOUT and the delay time τ2 from the fall of the input signal VIN to the rise of the output signal VOUT, three stages of inverters 13-1 to 13-3 Delay is obtained.

Next, the operation when the first mode signal VM1 is at the VCC level and the second mode signal VM2 is at the VSS level will be described. [VM1 = VCC, VM2 = VSS] When the first mode signal VM1 is at the VCC level, the NMOS transistors 28 of the first switch circuit 17-1 and the third switch circuit 17-3 are turned on, and the first switch circuit 17-1 and the third switch circuit 17-3 are turned on. Capacitor 15
-1 and the third capacitor 15-2 are connected to the first signal line 11A, respectively.

In this state, as shown in FIG. 16B, in particular, the output signal A is changed from the rise of the input signal VIN.
In addition to the delay due to the one stage of the inverter 13-1, the delay due to the discharge of the NMOS capacitor 25 of the third capacitor 15-3 is added to the fall.

Further, from the fall of the input signal VIN to the rise of the output signal A, the delay due to the one stage of the inverter 13-1 and the PMOS capacitor 2 of the first capacitor 15-1.
A delay due to the discharge of 6 is added.

Therefore, in the delay time τ1, the inverter 1
A delay obtained by discharging one NMOS capacitor 25 is added to the delay caused by the three stages of 3-1 to 13-3, and the delay time τ2 is the delay caused by the three stages of the inverters 13-1 to 13-3. One obtained by adding a delay due to discharge of one PMOS capacitor 26 is obtained.

Next, the operation when the first mode signal VM1 is at the VSS level and the second mode signal VM2 is at the VCC level will be described. [VM1 = VSS, VM2 = VCC] When the second mode signal VM2 is at the VCC level, the NMOS transistors 28 of the second switch circuit 17-2 and the fourth switch circuit 17-4 are turned on and the second switch circuit 17-2 and the second switch circuit 17-4 are turned on. Capacitor 15
-2 and the fourth capacitor 15-4 are connected to the second signal line 11B, respectively.

In this state, as shown in FIG. 14C, in particular, from the fall of the output signal A to the rise of the output signal B, to the delay by one stage of the inverter 13-2, to the second capacitor 15-. A delay due to the discharge of the second PMOS capacitor 26 is added.

Further, from the rise of the output signal VIN to the fall of the output signal B, the delay due to the one stage of the inverter 13-2, the NMOS capacitor 2 of the fourth capacitor 15-4.
A delay due to the discharge of 5 is added.

Therefore, in the delay time τ1, the inverter 1
A delay obtained by discharging one NMOS capacitor 25 is added to the delay caused by the three stages of 3-1 to 13-3, and the delay time τ2 is the delay caused by the three stages of the inverters 13-1 to 13-3. One obtained by adding a delay due to discharge of one PMOS capacitor 26 is obtained.

The operation when both the first mode signal VM1 and the second mode signal VM2 are at the VCC level will now be described. [VM1 = VCC, VM2 = VCC] Both the first mode signal VM1 and the second mode signal VM2 are VCC
At the level, the NMOS transistors 28 of the first switch circuit 17-1 to the fourth switch circuit 17-4 are turned on. Therefore, the first capacitor 15-1 and the third capacitor 15-2 are respectively connected to the first signal line 1
1A, the second capacitor 15-2 and the fourth capacitor 15-4 are connected to the second signal line 11B, respectively.

In this state, as shown in FIG. 14D, in particular, the output signal A is changed from the rise of the input signal VIN.
In addition to the delay due to the one stage of the inverter 13-1, the delay due to the discharge of the NMOS capacitor 25 of the third capacitor 15-3 is added to the fall.

Further, from the fall of the input signal VIN to the rise of the output signal A, the delay due to one stage of the inverter 13-1 and the PMOS capacitor 2 of the first capacitor 15-1.
A delay due to the discharge of 6 is added.

Further, from the fall of the output signal A to the rise of the output signal B, the delay due to one stage of the inverter 13-2, and the PMOS capacitor 26 of the second capacitor 15-2.
The delay due to the discharge of is added.

Further, from the rise of the output signal VIN to the fall of the output signal B, the delay due to one stage of the inverter 13-2, the NMOS capacitor 2 of the fourth capacitor 15-4.
A delay due to the discharge of 5 is added.

Therefore, the delay time τ1 and the delay time τ2
In both of the above, the delay obtained by discharging one NMOS capacitor 25 and the delay caused by discharging one PMOS capacitor 26 are added to the delay caused by the three stages of the inverters 13-1 to 13-3.

As described above, the device according to the ninth embodiment can make the delay time τ1 and the delay time τ2 larger than those of the devices according to the seventh and eighth embodiments. As described above, according to the devices according to the first to sixth embodiments, when the power supply voltage increases, the capacitor is automatically connected to the signal line and the delay time is extended. Therefore, it is possible to obtain a delay circuit having a small power supply voltage dependency. A semiconductor integrated circuit device having such a delay circuit operates normally even if the power supply voltage changes.

Further, in the semiconductor integrated circuit device having the delay circuit having a small power supply voltage dependency, the semiconductor integrated circuit device can be operated normally even when various power supply voltages are applied,
It is also possible to support various power supply voltages.

Further, according to the devices according to the seventh to ninth embodiments, one chip is used to automatically connect the capacitor to the signal line according to the operation mode and extend the delay time. It is possible to support various operation modes.

The conductivity types of the MOS capacitor of the capacitor 15 and the MOS capacitor of the switch circuit 17 are:
In addition to the above-mentioned embodiment, they can be freely combined. Further, when designing the devices according to the first to sixth embodiments, it is better to shift the design power supply voltage from the reference level P0. This is because the reference level P0 is a power supply voltage at which the delay time is switched, and therefore when the circuit is designed with this power supply voltage as the design power supply voltage, it is difficult to verify the original operation of the circuit. The design power supply voltage is preferably set higher than the reference level. By doing so, it becomes easy to verify the original operation of the circuit.

When the design power supply voltage is set to the center of the guaranteed range of the power supply voltage, the design power supply voltage corresponds to the voltage corresponding to the delay time displaced by the switching, and more preferably to the middle of the delay time displaced. It is good to choose a voltage.

For example, FIG. 10 shows a VCC center, which is a center within the guarantee range. FIG.
The voltage of the VCC center shown as 0 corresponds to a time τcent near the reference level P1 and between the minimum delay time τmin and the maximum delay time τmax.

By doing so, the deviation from the center of the guarantee range to the minimum delay time τmin and the deviation to the maximum delay time τmax can be equalized, and the circuit can be guaranteed within the guarantee range when designing an integrated circuit. It becomes easy to fit in.

[0171]

As described above, according to the present invention, a semiconductor integrated circuit device including a delay circuit capable of reducing the power supply voltage dependency of the delay time, and a delay circuit capable of changing the delay time according to the operation mode. And a semiconductor integrated circuit device including the above.

[Brief description of drawings]

FIG. 1 is a diagram showing a semiconductor integrated circuit device according to a first embodiment of the present invention, in which (a) is a block diagram and (b) is a block diagram.
The figure is a circuit diagram of the delay circuit, and the figure (c) is a circuit diagram of the detection circuit.

FIG. 2 is a diagram showing the relationship between the delay time and the power supply voltage of the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram of a delay circuit of a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 4 is a diagram showing a relationship between a delay time and a power supply voltage of a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a delay circuit of a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIG. 6 is a diagram showing a relationship between a delay time and a power supply voltage of a semiconductor integrated circuit device according to a third embodiment of the present invention,
FIG. 7A is a diagram showing the relationship when the potential of the signal line 11 is lowered, and FIG. 9B is a diagram showing the relationship when the potential of the signal line 11 is raised.

FIG. 7 is a circuit diagram of a delay circuit of a semiconductor integrated circuit device according to a fourth embodiment of the present invention.

FIG. 8 is a diagram showing a relationship between a delay time and a power supply voltage of a semiconductor integrated circuit device according to a fourth embodiment of the present invention.

9A and 9B are views showing a semiconductor integrated circuit device according to a fifth embodiment of the present invention, FIG. 9A is a block diagram, and FIG. 9B is a block diagram.
The figure is a circuit diagram of the delay circuit, and the figure (c) is a circuit diagram of the detection circuit.

FIG. 10 is a diagram showing the relationship between the delay time and the power supply voltage of the semiconductor integrated circuit device according to the fifth embodiment of the present invention.

FIG. 11 is a circuit diagram of a detection circuit of a semiconductor integrated circuit device according to a sixth embodiment of the present invention.

FIG. 12 is a block diagram of a semiconductor integrated circuit device according to a seventh embodiment of the present invention.

13 is a circuit diagram of the delay circuit shown in FIG.

14 is an operation waveform diagram of the delay circuit shown in FIG. 13, FIG. 14 (a) is an operation waveform diagram when VM1 = VSS, VM2 = VSS,
(B) The figure is the operation waveform diagram when VM1 = VCC, VM2 = VSS,
(C) The figure is an operation waveform diagram when VM1 = VSS, VM2 = VCC,
Figure (d) is an operation waveform diagram when VM1 = VCC, VM2 = VCC.

FIG. 15 is a circuit diagram of a delay circuit of a semiconductor integrated circuit device according to an eighth embodiment of the present invention.

16 is an operation waveform diagram of the delay circuit shown in FIG. 15, (a) is an operation waveform diagram when VM1 = VSS, VM2 = VSS,
(B) The figure is the operation waveform diagram when VM1 = VCC, VM2 = VSS,
(C) The figure is an operation waveform diagram when VM1 = VSS, VM2 = VCC,
Figure (d) is an operation waveform diagram when VM1 = VCC, VM2 = VCC.

FIG. 17 is a circuit diagram of a delay circuit of a semiconductor integrated circuit device according to a ninth embodiment of the present invention.

18 is an operation waveform diagram of the delay circuit shown in FIG. 17, FIG. 18 (a) is an operation waveform diagram when VM1 = VSS, VM2 = VSS,
(B) The figure is the operation waveform diagram when VM1 = VCC, VM2 = VSS,
(C) The figure is an operation waveform diagram when VM1 = VSS, VM2 = VCC,
Figure (d) is an operation waveform diagram when VM1 = VCC, VM2 = VCC.

FIG. 19 is a circuit diagram of a conventional delay circuit.

FIG. 20 is a diagram showing a relationship between delay time and power supply voltage.

[Explanation of symbols]

1 ... Delay circuit, 9 ... Power supply voltage fluctuation detection circuit, 11, 11
A, 11B ... Output signal line, 13, 13-1, 13-2, 13
-3 ... CMOS type inverter, 15 ... Capacitor, 17 ...
Switch circuit, 21, 21-1, 21-2, 21-3 ... P-channel type MOS transistor, 23, 23-1, 23-2, 2
3-3 ... N-channel type MOS transistor, 25 ... N-channel type MOS capacitor, 26 ... P-channel type MOS capacitor, 27 ... P-channel type MOS transistor, 2
8 ... N-channel type MOS transistor, 31 ... Voltage dividing circuit, 33, 35 ... Inverter, 41, 43 ... Resistor.

Claims (11)

[Claims] 1. A delay circuit including a wiring and a capacitance circuit connected to the wiring, and an amount of current flowing through a current path connecting the wiring and the capacitance circuit is adjusted to reduce a delay time of the delay circuit. A semiconductor integrated circuit device, comprising: a delay time changing circuit for changing. 2. A detection circuit for detecting fluctuations in power supply voltage, a capacitance circuit, and a coupling circuit for coupling the capacitance circuit to one wiring in the circuit according to an output signal of the detection circuit. A characteristic semiconductor integrated circuit device. 3. A mode circuit for defining an operation mode of an integrated circuit, a capacitance circuit, and a coupling circuit for coupling the capacitance circuit to one wiring in the circuit according to an output signal of the mode circuit. A semiconductor integrated circuit device. 4. A semiconductor integrated circuit comprising: a detection circuit for detecting a fluctuation of a power supply voltage; and a delay circuit for receiving an output signal of the detection circuit and changing a delay time according to the output signal. apparatus. 5. A semiconductor integrated circuit comprising: a mode circuit that defines an operation mode of the integrated circuit; and a delay circuit that receives an output signal of the mode circuit and changes a delay time according to the output signal. Circuit device. 6. A logic circuit, a wiring connected to the output of the logic circuit, an insulated gate FET in which one of a drain and a source is connected to the wiring, and the other of the drain and the source of the insulated gate FET. And a capacitor having one electrode connected thereto, the amount of current flowing between the source and drain of the gate of the insulated gate FET is adjusted according to a signal input to the gate of the insulated gate FET. A semiconductor integrated circuit device, wherein a capacitance coupled to the wiring is changed. 7. A detection circuit for detecting a fluctuation of a power supply voltage, a logic circuit, a wiring connected to an output of the logic circuit, and one of a drain and a source connected to the wiring, and a gate for the detection circuit. An insulated gate FET to which an output signal of the circuit is input, and a capacitor having one electrode connected to the other of the drain and the source of the insulated gate FET are provided, and the capacitor is provided according to the output signal of the detection circuit. Insulated gate type F
Adjust the amount of current that can flow between the source and drain of ET,
A semiconductor integrated circuit device, wherein a capacitance coupled to the wiring is changed. 8. A mode circuit for defining an operation mode of an integrated circuit, a logic circuit, a wiring connected to an output of the logic circuit, and one of a drain and a source connected to the wiring and a gate An insulated gate FET to which an output signal of the mode circuit is input, and a capacitor having one electrode connected to the other of the drain and the source of the insulated gate FET are provided, and according to the output signal of the mode circuit, A semiconductor integrated circuit device, wherein the amount of current flowing between the source and the drain of the insulated gate FET is adjusted to change the capacitance coupled to the wiring. 9. A logic circuit, and a coupling circuit for coupling a capacitance to an output wiring of the logic circuit, the amount of current flowing through the coupling circuit is adjusted to change the capacitance of the output wiring, Rise time of output of logic circuit,
A semiconductor integrated circuit device, characterized in that any one of the above and the fall time is changed. 10. A logic circuit and a coupling circuit for coupling a capacitance to an output wiring of the logic circuit, wherein the power supply voltage is higher than a reference level, the power supply voltage is lower than the reference level. The capacity of the output wiring is changed so that the coupling circuit can flow more current, and either the rising time or the falling time of the output signal of the logic circuit is changed according to the level of the power supply voltage. A semiconductor integrated circuit device characterized by the above. 11. A first state, comprising: a logic circuit; and a coupling circuit for coupling a capacitance to an output wiring of the logic circuit, wherein the coupling circuit has a large amount of current that can flow.
The second state in which the amount of current that the coupling circuit can flow is smaller than the first state is obtained, and the capacitance of the output wiring is changed between the first state and the second state. The semiconductor integrated circuit device is characterized in that either the rising time or the falling time of the output signal of the logic circuit is changed by selecting one of the state 1 and the second state.