JPH10145044A - Multilayer printed wiring board - Google Patents

Multilayer printed wiring board

Info

Publication number
JPH10145044A
JPH10145044A JP8315655A JP31565596A JPH10145044A JP H10145044 A JPH10145044 A JP H10145044A JP 8315655 A JP8315655 A JP 8315655A JP 31565596 A JP31565596 A JP 31565596A JP H10145044 A JPH10145044 A JP H10145044A
Authority
JP
Japan
Prior art keywords
heat
holes
wiring board
hole
printed wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8315655A
Other languages
Japanese (ja)
Inventor
Kazumitsu Ishikawa
和充 石川
Harumi Kubota
春實 久保田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lincstech Circuit Co Ltd
Original Assignee
Hitachi AIC Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi AIC Inc filed Critical Hitachi AIC Inc
Priority to JP8315655A priority Critical patent/JPH10145044A/en
Publication of JPH10145044A publication Critical patent/JPH10145044A/en
Pending legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To raise the mounting density and wiring pattern density in a high soldering heat-resistive environment by providing continuity connection holes in land layer regions for soldering electrodes of flat mounting components and charging a high thermal conductivity and heat-resistive thermosetting resin in the connection holes. SOLUTION: On the front and back sides of a laminate substrate 1 outer and inner conductors 2, 3 are formed and laminate 1 is laid to form a printed multilayer wiring board 19. Through-holes 4 are formed through this board 19 and a uniform Cu plating layer 5 is formed on the inner walls 4a of the holes 4 and front and back sides of the outer and dinner layers conductors 2, 3 to form continuity connection holes 9 in which a high-thermal conductive resin paste 16 is then charged and pre-dried and undesired paste 16 on the tops of the connection holes 9 is planarized and removed, it is hardened. On the connection holes 9, flat mounting components 15 are mounted by high temp. soldering. This reduces the connection hole land regions 18 and raises the mounting density and wiring density.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、面実装部品を高密
度に実装できる両面または多層プリント配線板の構造に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a double-sided or multilayer printed wiring board on which surface-mounted components can be mounted at a high density.

【0002】[0002]

【従来の技術】近年は、電子部品の小形化、高密度実装
化に伴い、面実装部品をより一層高密度な実装ができる
ように一段と進展している。以下、図5(a)〜
(b)、図6(c)〜(e)及び図7(f)〜(g)に
基づき、従来の技術に係るプリント配線板39の製造工
程を説明する。
2. Description of the Related Art In recent years, with the miniaturization and high-density mounting of electronic components, progress has been made further so that surface-mounted components can be mounted at even higher densities. Hereinafter, FIGS.
The manufacturing process of the printed wiring board 39 according to the prior art will be described with reference to (b), FIGS. 6 (c) to (e), and FIGS. 7 (f) to (g).

【0003】先ず、2層以上の配線層を有した積層基板
21を用いて、この積層基板21を外層導体22におい
て、積層化したガラスエポキシ樹脂多層プリント配線板
39を用い(a図)、この多層プリント配線板39に選
択的に貫通孔24を穿設する(b図)。
[0003] First, using a laminated substrate 21 having two or more wiring layers, using a laminated glass epoxy resin multilayer printed wiring board 39 with the laminated substrate 21 laminated on an outer conductor 22 (FIG. 1A). The through holes 24 are selectively formed in the multilayer printed wiring board 39 (FIG. 2B).

【0004】次に、化学めっきと電気めっきとの併用法
により、上記貫通孔24の孔内壁24A、内層導体層2
3及び外層導体層22の表裏層全面上に第1銅層25を
施し、導通接続孔32を形成する(c図)。次に上記導
通接続孔32の孔内に熱硬化性樹脂(エポキシ)26を
充填熱硬化し、第1の銅層25の表面と平滑にする(d
図)。次に電気めっき法により第2の銅層27を形成す
る(e図)。
Next, the inner wall 24A of the through hole 24 and the inner conductor layer 2 are formed by a combined method of chemical plating and electroplating.
The first copper layer 25 is formed on the entire surface of the front and back layers of the third and outer conductor layers 22 to form the conductive connection holes 32 (FIG. 3C). Next, a thermosetting resin (epoxy) 26 is filled into the holes of the conductive connection holes 32 and heat-cured to smooth the surface of the first copper layer 25 (d)
Figure). Next, a second copper layer 27 is formed by electroplating (FIG. 5E).

【0005】次いで、上記第2の銅層27表面に公知の
感光性ドライフィルム(感光層厚み50μm)37をラ
ミネートとし、その表面に配線パターン用ネガマスク2
8を用いて、UV露光29をする(f図)。更に、アル
カリ現像、エッチング工程により、不用な領域の銅めっ
き層25,27と外層導体層22を除去し所望の広い領
域38のスルーホールランド33,34及び導体パター
ン30,31形成が得られる(g図)。
Next, a known photosensitive dry film (photosensitive layer thickness: 50 μm) 37 is laminated on the surface of the second copper layer 27, and a negative mask 2 for a wiring pattern is formed on the surface.
Then, UV exposure 29 is performed using FIG. 8 (f figure). Further, the unnecessary portions of the copper plating layers 25 and 27 and the outer conductor layer 22 are removed by an alkali developing and etching process, and the formation of the through-hole lands 33 and 34 and the conductor patterns 30 and 31 in a desired wide area 38 can be obtained ( g figure).

【0006】図8に示すように広い領域38のスルーホ
ールランド33,34と面実装部品15の半田付(リフ
ロー炉)の際に導通接続孔32の孔内の熱硬化性樹脂2
6が半田耐熱により樹脂26の熱膨張膨れ36が発生
し、第2スルーホールランド層の膨れ35が生じ、面実
装部品15の電気的接続信頼性と多層プリント配線板3
9の実装面積を有効に活用することにおいて、問題が生
じ得る。また、前記の製造技術(スルーホールランド構
成)について、特公平8−31695の文献に記載され
ている。
[0008] As shown in FIG. 8, when the through holes lands 33, 34 in the wide area 38 and the surface mount component 15 are soldered (reflow furnace), the thermosetting resin 2 in the holes of the conductive connection holes 32 is soldered.
6, the thermal expansion swelling 36 of the resin 26 occurs due to the heat resistance of the solder, the swelling 35 of the second through-hole land layer occurs, and the electrical connection reliability of the surface mount component 15 and the multilayer printed wiring board 3
A problem may arise in utilizing the mounting area of No. 9 effectively. Further, the above manufacturing technique (through-hole land configuration) is described in Japanese Patent Publication No. 8-31695.

【0007】[0007]

【発明が解決しようとする課題】しかしながら前記技術
では、高密度実装のリフロー炉半田付性及び高密度化の
ための多層プリント配線板39の実装面積をより一層有
効に活用することについて、以下のような課題をもって
いる。
However, according to the above-mentioned technology, the following problems have been solved in that the solderability of the reflow furnace for high-density mounting and the mounting area of the multilayer printed wiring board 39 for higher density are more effectively utilized. Have such issues.

【0008】その第1としては、図8に示すように最近
のリフロー炉半田付環境は、半田溶融温度が高温条件と
なり、導通接続孔32の孔内に形成した熱硬化性樹脂2
6、例えばエポキシ樹脂26が高温半田耐熱により熱膨
張膨れ(170℃、転移温度)36が生じ、第2スルー
ホールランド層の膨れ35現象が起り、そのために一方
端の面実装部品15が立ち上がり電気的接続信頼性に問
題がある。
First, as shown in FIG. 8, in a recent reflow furnace soldering environment, the solder melting temperature is set to a high temperature condition, and the thermosetting resin 2 formed in the conductive connection hole 32 is formed.
6. For example, the epoxy resin 26 undergoes thermal expansion and swelling (170 ° C., transition temperature) 36 due to high-temperature soldering heat resistance, causing a swelling 35 phenomenon of the second through-hole land layer. Connection reliability is problematic.

【0009】その第2としては、面実装部品15用スル
ーホールランド層33,34が広い領域38で構成さ
れ、またランド層33,34の厚みも50〜55μmと
厚く構成されている。従って、多層プリント配線板39
の実装面積を有効に活用し、高密度実装化の進展に問題
が生ずる。またランド層33,34が厚いために、公知
のサイドエッチング量が大きくなり、公知のランドレス
化が困難という課題がある。
Second, the through-hole land layers 33, 34 for the surface mount component 15 are formed of a wide area 38, and the land layers 33, 34 are also formed to have a large thickness of 50 to 55 μm. Therefore, the multilayer printed wiring board 39
This makes effective use of the mounting area, and causes a problem in the development of high-density mounting. In addition, since the land layers 33 and 34 are thick, a known side etching amount becomes large, and there is a problem that it is difficult to form a known landless.

【0010】したがって、本発明は上記の問題を解消
し、高温半田耐熱の環境下において高密度実装化及び配
線パターン11の高密度化できる多層プリント配線板1
9を提供することを目的とするものである。
Accordingly, the present invention solves the above-mentioned problems and provides a multilayer printed wiring board 1 capable of high-density mounting and high-density wiring patterns 11 in an environment of high-temperature soldering heat resistance.
9 is intended to be provided.

【0011】[0011]

【課題を解決するための手段】本発明は、上記の目的を
達成するために、多層プリント配線板19の表裏面また
は内層導体3に導通する導通接続孔9が面実装部品15
の電極部14を半田付けするためのランド層8領域内に
設けられ、
According to the present invention, in order to achieve the above-mentioned object, a conductive connection hole 9 for conducting to the front and back surfaces of a multilayer printed wiring board 19 or the inner layer conductor 3 is provided.
Is provided in a land layer 8 region for soldering the electrode portion 14 of

【0012】かつ熱伝導体の大きい耐熱性熱硬化性樹脂
12に金属粉10を含有してなる導電性樹脂ペースト1
6を用い、前記導通接続孔9の孔内に充填形成し、この
孔9上に面実装部品15を半田付けでき得る高密度実装
多層プリント配線板19を提供するものである。
A conductive resin paste 1 comprising a metal powder 10 in a heat-resistant thermosetting resin 12 having a large heat conductor.
6, a high-density mounting multilayer printed wiring board 19 capable of being formed by filling the hole of the conductive connection hole 9 and soldering the surface mounting component 15 onto the hole 9.

【0013】[0013]

【発明の実施の形態】本発明は、上記の構成によると耐
熱性ポリイミド樹脂HI−L12に導電性金属粉10を
含有してなる導電性樹脂ペースト16を用いて、導通接
続孔9の孔内に充填、形成し、かつ前記の導通接続孔9
の孔上に容易に面実装部品15を実装、半田付けでき、
また前記のランド層8が第1の銅層5のみで形成できる
ため、配線の高密度化がより一層高密度実装を実現でき
得るものである。
DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the present invention, a conductive resin paste 16 comprising a heat-resistant polyimide resin HI-L12 and a conductive metal powder 10 is used to form a conductive connection hole 9 in a hole. And the conductive connection hole 9
The surface mount component 15 can be easily mounted and soldered on the hole of
Further, since the land layer 8 can be formed only of the first copper layer 5, the wiring density can be further increased to realize a higher density mounting.

【0014】[0014]

【実施例】本発明の実施例を示す図2(a)〜(b)、
図3(c)〜(e)及び図4(f)に基づいて、具体的
に説明する。
2A and 2B showing an embodiment of the present invention.
This will be specifically described based on FIGS. 3C to 3E and 4F.

【0015】[0015]

【実施例1】まず、図2(a)は、両面以上の配線層
2,3を有した積層基板1であり、この積層基板1は、
その最外層の表裏を外層導体2で構成しており、その厚
さ約1.6mmは、例えば、ガラス基材にエポキシ樹脂を
含浸して多層接着した最外層銅箔からなるプリント多層
配線板19等の公知挙げられる。
Embodiment 1 First, FIG. 2A shows a laminated substrate 1 having wiring layers 2 and 3 on both sides or more.
The outermost layer of the outermost layer is formed of the outer layer conductor 2 and has a thickness of about 1.6 mm. And the like.

【0016】次に、図2(b)に示すように、例えばφ
0.6mmドリルを使い、選択的に貫通孔4を穿設(日立
高精度孔明機.MARK100)する。この穿設する工
法は、例えばドリリング、プラズマ、レーザー加工、プ
レス等の公知挙げられる。
Next, as shown in FIG.
Using a 0.6 mm drill, the through hole 4 is selectively drilled (Hitachi high precision drilling machine. MARK100). Examples of the method of forming the hole include known methods such as drilling, plasma, laser processing, and press.

【0017】次に、図3(c)に示すように、上記貫通
孔4の孔内壁4A、内装導体3及び外層導体2表裏面上
に均一な膜厚20〜25μm銅めっき層5を形成し、か
つ導通接続孔9(以下、スルーホールと記す。)を形成
する。この銅めっき法は、例えば、無電解めっき法、無
電解めっきと電気めっきとの併用法、プラズマ法、熱溶
解法など、公知挙げられる。
Next, as shown in FIG. 3 (c), a copper plating layer 5 having a uniform film thickness of 20 to 25 μm is formed on the inner wall 4A of the through hole 4, the inner conductor 3 and the outer conductor 2 on the front and back surfaces. And conductive connection holes 9 (hereinafter referred to as through holes). Known examples of the copper plating method include an electroless plating method, a combined use method of electroless plating and electroplating, a plasma method, and a thermal melting method.

【0018】次に、図3(d)に示すように上記スルー
ホール9孔内に本発明の導電性樹脂ペースト16(粒径
4〜11μmの銅粉約84wt%と残部が耐熱性ポリイミ
ド樹脂12で日立化成工業株式会社製 商品名:HI−
L)を選択的にスキージを用いて、充填し約80℃で導
電性樹脂ペースト16の仮乾燥を行い、更に、スルーホ
ール9孔上部の不要導電性樹脂ペースト16を研摩機で
平坦化除去後、170℃の乾燥炉等で本硬化する。この
耐熱性ポリイミド樹脂(HI−L)12は、下記内容の
特長を有している。
Next, as shown in FIG. 3D, the conductive resin paste 16 of the present invention (about 84 wt% of copper powder having a particle size of 4 to 11 μm and the remainder is heat-resistant polyimide resin 12 Made by Hitachi Chemical Co., Ltd. Product name: HI-
L) is selectively filled using a squeegee, the conductive resin paste 16 is temporarily dried at about 80 ° C., and the unnecessary conductive resin paste 16 above the through holes 9 is flattened and removed by a polishing machine. And in a drying oven at 170 ° C. The heat-resistant polyimide resin (HI-L) 12 has the following features.

【0019】以下に、その第1、第2及び第3として記
載する。先ず、その第1としては、低沸点溶剤に可溶で
ある。つまり、HI−Lはアセトン、メチルエチルケト
ンなどの低沸点溶剤に可溶である。このために塗布、充
填製造時の乾燥温度の範囲が広くなるため、反応度合の
制御が容易であり、エポキシ樹脂と同様の作業ができ
る。
Hereinafter, the first, second and third aspects will be described. First, it is soluble in low-boiling solvents. That is, HI-L is soluble in low-boiling solvents such as acetone and methyl ethyl ketone. For this reason, since the range of the drying temperature at the time of coating and filling production is widened, the degree of reaction can be easily controlled, and the same operation as the epoxy resin can be performed.

【0020】その第2としては、硬化性が優れている。
つまり、HI−L12は、エポキシ樹脂と同様に170
℃、60分で硬化し、この硬化した本発明の樹脂12の
転移温度は、320℃程である。従って半田耐熱約26
0℃、リフロー炉3回通す環境下において、スルーホー
ル9孔内の樹脂膨れ36現象は発生しない特徴を有して
いる。その第3としては、熱伝導体(10-4cal/sec)
5.2〜5.8を有している。
Second, the curability is excellent.
That is, HI-L12 is 170
The resin 12 is cured at 60 ° C. for 60 minutes, and the transition temperature of the cured resin 12 of the present invention is about 320 ° C. Therefore, the solder heat resistance is about 26.
Under an environment of passing through a reflow furnace three times at 0 ° C., the resin swelling 36 in the through holes 9 does not occur. Third, thermal conductor (10 -4 cal / sec)
5.2 to 5.8.

【0021】更に、図3(e)に示すように、公知の感
光性ドライフィルム17(日立化成工業株式会社製、商
品名:N−24(40μm))をラミネートとし、ネガ
マスク6を使いUV露光7を行い、
Further, as shown in FIG. 3E, a known photosensitive dry film 17 (manufactured by Hitachi Chemical Co., Ltd., trade name: N-24 (40 μm)) is laminated, and UV exposure is performed using a negative mask 6. Perform 7

【0022】その後、図4(f)に示すように、無水炭
酸ソーダ(1wt%−Na2CO3水溶液)で現象を行
い、次いで、塩化第2鉄液を用いて、エッチング剥離
(2.5〜3.0wt%、苛性ソーダ水溶液)を行い、ス
ルーホールランド領域18が小さく、半田付耐熱性用所
望の多層プリント配線板19が得られる。
Thereafter, as shown in FIG. 4 (f), the phenomenon is carried out with anhydrous sodium carbonate (1 wt% -Na2CO3 aqueous solution), and then, etching stripping (2.5-3. (Aqueous sodium hydroxide solution of 0 wt%), the through-hole land area 18 is small, and a desired multilayer printed wiring board 19 for heat resistance to soldering is obtained.

【0023】図1に示すように、本発明の実施例であ
り、この実施例のスルーホール9孔上部に面実装部品1
5を半田付けした後の多層プリント配線板19の断面図
であり、また高耐熱性導電性ペースト16を用い、スル
ーホール9孔上に面実装部品15が高温半田付けでき、
かつ多層プリント配線板19の実装に面積が有効に活用
できることを特徴とするものである。
As shown in FIG. 1, this is an embodiment of the present invention.
FIG. 5 is a cross-sectional view of the multilayer printed wiring board 19 after soldering No. 5, and using a high heat-resistant conductive paste 16, the surface mount component 15 can be soldered at a high temperature on the through-hole 9;
In addition, the area can be effectively used for mounting the multilayer printed wiring board 19.

【0024】[0024]

【発明の効果】以上説明したように、本発明によれば、
耐熱性ポリイミド樹脂導電性ペースト16を用いること
で、高温環境下において半田付けが可能となり、また実
装面積も有効に活用可能となったため、以下に記載する
特有な効果を奏する。
As described above, according to the present invention,
By using the heat-resistant polyimide resin conductive paste 16, soldering can be performed in a high-temperature environment, and the mounting area can be effectively utilized. Therefore, the following specific effects can be obtained.

【0025】(1)本発明によれば、本発明の高耐熱性
導電性ペースト16を用いることにより、面実装部品1
5の半田付けスルーホールランド8は第1銅めっき層5
のみで形成し、またスルーホール9孔上にも半田付け可
能なためにスルーホールランド領域18が小さくでき高
密度実装化及び配線高密度化が実現可能な多層プリント
配線板19を発明でき、産業上寄与する効果は極めて大
きい。
(1) According to the present invention, the surface-mounted component 1 is formed by using the highly heat-resistant conductive paste 16 of the present invention.
5 solder through-hole land 8 is the first copper plating layer 5
It is possible to invent a multi-layer printed wiring board 19 which can be formed with only the through-hole 9 and can be soldered on the through-hole 9 so that the through-hole land area 18 can be reduced and high-density mounting and high-density wiring can be realized. The effect contributing above is extremely large.

【0026】(2)本発明によれば、耐熱性ポリイミド
樹脂HI−L12を用いてスルーホール9孔内に充填、
形成しているため、面実装部品15を半田付ける際に
(リフロー炉を通す場合)スルーホール9孔内の充填樹
脂12の膨れ36現象が発生しないため、電極部14の
電気的接続信頼性が確保でき得る。
(2) According to the present invention, the heat-resistant polyimide resin HI-L12 is used to fill the through holes 9 with
Because of this, when soldering the surface mount component 15 (when passing through a reflow furnace), the swelling 36 of the filling resin 12 in the through-hole 9 does not occur, so that the electrical connection reliability of the electrode portion 14 is improved. Can be secured.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の多層プリント配線板に面実装部品を実
装した状態を示す断面図。
FIG. 1 is a sectional view showing a state in which a surface mount component is mounted on a multilayer printed wiring board according to the present invention.

【図2】(a)〜(b)は、本発明の製造工程を示す断
面図。
FIGS. 2A and 2B are cross-sectional views illustrating a manufacturing process of the present invention.

【図3】(c)〜(e)は、本発明の製造工程を示す断
面図。
FIGS. 3 (c) to 3 (e) are cross-sectional views illustrating a manufacturing process of the present invention.

【図4】(f)は、本発明の製造工程を示す断面図。FIG. 4 (f) is a sectional view showing a manufacturing step of the present invention.

【図5】(a)〜(b)は、従来の製造工程を示す断面
図。
FIGS. 5A and 5B are cross-sectional views showing a conventional manufacturing process.

【図6】(c)〜(e)は、従来の製造工程を示す断面
図。
FIGS. 6C to 6E are cross-sectional views showing a conventional manufacturing process.

【図7】(f)〜(g)は、従来の製造工程を示す断面
図。
FIGS. 7F to 7G are cross-sectional views showing a conventional manufacturing process.

【図8】従来の技術を示す断面図。FIG. 8 is a sectional view showing a conventional technique.

【符号の説明】[Explanation of symbols]

1…積層基板 2…外層導体(配線層) 3…内装導体
(配線層) 4…貫通孔 4A…孔内壁 5…第1銅めっき層 6…
マスク(ネガ) 7…UV露光 8…ランド層 9…導通接続孔 10…
金属粉 11…導体パターン 12…耐熱性熱硬化性樹脂 13
…半田 14…電極部 15…面実装部品 16…導電性樹脂ペースト 17…
感光性ドライフィルム 18…スルーホールランド領域 19…本発明の多層プ
リント配線板 21…積層基板 22…外層導体層 23…内層導体層
24…貫通孔 24A…孔内壁 25…第1の銅層 26…熱硬化性樹
脂 27…第2の銅層 28…マスク(ネガ) 29…UV露光 30…第1導
体パターン 31…第2導体パターン 32…導通接続孔 33…第
1スルーホールランド 34…第2スルーホールランド 35…第2スルーホー
ル層の膨れ 36…熱膨張膨れ 37…感光性ドライフィルム 38…スルーホールランド領域 39…従来の多層プリ
ント配線板
DESCRIPTION OF SYMBOLS 1 ... Laminated board 2 ... Outer layer conductor (wiring layer) 3 ... Interior conductor (wiring layer) 4 ... Through-hole 4A ... Hole inner wall 5 ... 1st copper plating layer 6 ...
Mask (negative) 7 UV exposure 8 Land layer 9 Conducting connection hole 10
Metal powder 11: Conductive pattern 12: Heat-resistant thermosetting resin 13
... Solder 14 ... Electrode part 15 ... Surface mount component 16 ... Conductive resin paste 17 ...
Photosensitive dry film 18 through-hole land area 19 multilayer printed wiring board 21 of the present invention 21 laminated substrate 22 outer conductor layer 23 inner conductor layer 24 through hole 24A inner wall 25 first copper layer 26 Thermosetting resin 27 ... second copper layer 28 ... mask (negative) 29 ... UV exposure 30 ... first conductor pattern 31 ... second conductor pattern 32 ... conduction connection hole 33 ... first through hole land 34 ... second through Hole land 35: swelling of second through-hole layer 36: thermal expansion swelling 37: photosensitive dry film 38: through-hole land area 39: conventional multilayer printed wiring board

【手続補正書】[Procedure amendment]

【提出日】平成8年11月29日[Submission date] November 29, 1996

【手続補正1】[Procedure amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0015[Correction target item name] 0015

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【0015】[0015]

【実施例1】まず、図2(a)は、両面以上の配線層
2,3を有した積層基板1であり、この積層基板1は、
その最外層の表裏を外層導体2で構成しており、その厚
さ約1.6mmは、例えば、ガラス基材にエポキシ樹脂
を含浸して多層接着した最外層銅箔からなる多層プリン
ト配線板19等の公知挙げられる。
Embodiment 1 First, FIG. 2A shows a laminated substrate 1 having wiring layers 2 and 3 on both sides or more.
The outermost layer of the outermost layer is made of an outer layer conductor 2 and has a thickness of about 1.6 mm, for example, a multilayer printed circuit made of an outermost layer copper foil in which a glass base material is impregnated with epoxy resin and bonded in multiple layers.
Known wiring board 19 and the like.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 両面以上の配線層(2,3)を有した積
層基板(1)を用いて、この積層基板(1)に貫通孔
(4)を有し、かつ、銅めっき層(5)からなる導通接
続孔(9)及びランド層(8)を有する多層プリント配
線板(19)において、前記導通接続孔(9)内を、少
なくとも一方の露出面が半田付性を有する充填物、この
充填物は熱伝導体が大きく、かつ、耐熱性熱硬化性樹脂
(12)で充填してなることを特徴とする多層プリント
配線板(19)。
A laminated board (1) having wiring layers (2, 3) on both sides or more is used. The laminated board (1) has a through hole (4) and a copper plating layer (5). In the multilayer printed wiring board (19) having a conductive connection hole (9) and a land layer (8), at least one exposed surface of the conductive connection hole (9) has a solderability. This filler has a large heat conductor and is filled with a heat-resistant thermosetting resin (12).
【請求項2】 請求項1において、上記耐熱性熱硬化性
樹脂(12)は、導電性と半田付性を有する材料からな
り、この材料は、耐熱性ポリイミド樹脂(12)で金属
粉(10)を含有する導電性樹脂ペース(16)からな
ることを特徴とする多層プリント配線板(19)。
2. The heat-resistant thermosetting resin (12) according to claim 1, wherein the heat-resistant thermosetting resin (12) is made of a material having conductivity and solderability, and is made of a heat-resistant polyimide resin (12). (19) A multilayer printed wiring board (19) comprising a conductive resin paste (16) containing:
【請求項3】 請求項2において、上記金属粉(10)
が銀、ニッケル及び銅からなる群より選択した少なくと
も1つの金属元素からなることを特徴とする多層プリン
ト配線板(19)。
3. The metal powder (10) according to claim 2, wherein
Is composed of at least one metal element selected from the group consisting of silver, nickel and copper.
JP8315655A 1996-11-13 1996-11-13 Multilayer printed wiring board Pending JPH10145044A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8315655A JPH10145044A (en) 1996-11-13 1996-11-13 Multilayer printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8315655A JPH10145044A (en) 1996-11-13 1996-11-13 Multilayer printed wiring board

Publications (1)

Publication Number Publication Date
JPH10145044A true JPH10145044A (en) 1998-05-29

Family

ID=18067993

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8315655A Pending JPH10145044A (en) 1996-11-13 1996-11-13 Multilayer printed wiring board

Country Status (1)

Country Link
JP (1) JPH10145044A (en)

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