JPH11233893A - Semiconductor light emitting device and method of manufacturing the same - Google Patents

Semiconductor light emitting device and method of manufacturing the same

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Publication number
JPH11233893A
JPH11233893A JP3563898A JP3563898A JPH11233893A JP H11233893 A JPH11233893 A JP H11233893A JP 3563898 A JP3563898 A JP 3563898A JP 3563898 A JP3563898 A JP 3563898A JP H11233893 A JPH11233893 A JP H11233893A
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JP
Japan
Prior art keywords
light emitting
region
emitting device
layer
continuous film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3563898A
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Japanese (ja)
Other versions
JPH11233893A5 (en
JP4169821B2 (en
Inventor
Mototaka Tanetani
元隆 種谷
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Sharp Corp
Original Assignee
Sharp Corp
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Abstract

(57)【要約】 【課題】 部分的成長抑制構造を利用して、基板と格子
定数または熱膨張係数が異なる連続膜半導体層を形成し
た上に、さらに半導体発光素子を形成する場合の発光効
率の低下および信頼性の悪化を防止する。 【解決手段】 成長抑制構造上への結晶成長により得ら
れる成長抑制構造上方領域を含む連続膜半導体層の上に
形成された半導体発光素子において、活性層の内、電流
注入により光を発生する発光領域が上記成長抑制構造上
方領域以外の領域に形成されているようにする。
(57) Abstract: A luminous efficiency when a semiconductor light emitting element is further formed on a continuous film semiconductor layer having a lattice constant or a thermal expansion coefficient different from that of a substrate using a partial growth suppressing structure. And reliability are prevented from deteriorating. SOLUTION: In a semiconductor light emitting device formed on a continuous film semiconductor layer including a region above a growth suppressing structure obtained by crystal growth on a growth suppressing structure, light emission which generates light by current injection in an active layer. The region is formed in a region other than the region above the growth suppressing structure.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体発光素子に
関し、特に、基板上に基板とは格子定数または熱膨張係
数の異なる半導体材料にて形成された信頼性の高い半導
体発光素子に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light emitting device, and more particularly to a highly reliable semiconductor light emitting device formed on a substrate with a semiconductor material having a different lattice constant or thermal expansion coefficient from the substrate.

【0002】[0002]

【従来の技術】半導体発光素子を構成する結晶材料とは
格子定数が3%以上異なる基板上へ形成する場合や、熱
膨張係数が10%以上異なる基板上へ半導体結晶を成長
する場合には、まず基板の上に半導体発光素子を構成す
る材料と格子定数や熱膨張係数がほぼ等しい(格子定
数、熱膨張係数とも1%以内)結晶材料を厚く成長させ
連続膜半導体層を形成した上に半導体発光素子を形成す
る試みがなされている。連続膜半導体層の上に積層した
半導体層は結晶欠陥が低減することが報告されている。
このような発光素子の代表例として、図8に、サファイ
ア基板800上に、GaN層を厚く結晶成長させて連続
膜半導体層を形成し、その上に青色発光ダイオード(L
ED)を形成した従来技術による例を示す。
2. Description of the Related Art When a semiconductor light emitting device is formed on a substrate having a lattice constant different from the crystal material by 3% or more, or when a semiconductor crystal is grown on a substrate having a thermal expansion coefficient different by 10% or more, First, a crystal material having a lattice constant and a coefficient of thermal expansion substantially equal to those of the material constituting the semiconductor light emitting device (both within 1% in both the lattice constant and the coefficient of thermal expansion) is grown on the substrate to form a continuous film semiconductor layer. Attempts have been made to form light emitting elements. It has been reported that a semiconductor layer stacked on a continuous film semiconductor layer has reduced crystal defects.
As a typical example of such a light emitting device, FIG. 8 shows that a GaN layer is grown thickly on a sapphire substrate 800 to form a continuous film semiconductor layer, and a blue light emitting diode (L) is formed thereon.
An example according to the prior art in which ED) is formed is shown.

【0003】この従来例のLEDの作製方法を説明す
る。サファイア基板800上に、まずハライド気相成長
法(HVPE法)によりGaN層801を5μm厚に厚
く成長させる。次に、GaN層801表面にSiO2
らなる選択成長マスク802を格子状(200μmピッ
チの20μm幅のSiO2ストライプが互いに直交する
形)に形成する。以上までに作製された工程断面図を図
8(a)に示す。
A method of manufacturing this conventional LED will be described. First, a GaN layer 801 is grown to a thickness of 5 μm on the sapphire substrate 800 by a halide vapor deposition method (HVPE method). Next, a selective growth mask 802 made of SiO 2 is formed on the surface of the GaN layer 801 in a lattice shape (a shape of SiO 2 stripes of 200 μm pitch and 20 μm width is orthogonal to each other). FIG. 8A is a cross-sectional view of the process manufactured as described above.

【0004】次に、このサファイア基板800上にHV
PE法によりn型GaN連続膜半導体層803を300
μm厚成長させる。この時、HVPE工程により成長さ
れたn型GaN連続膜半導体層803は、サファイア基
板800が露出した部分から成長が始まるが、その厚さ
が増すに伴い、SiO2からなる選択成長用マスク80
2上へ張り出すように左右へも成長し、最終的には20
μm幅のSiO2からなる選択成長マスク802上を覆
った。このようにして、表面が平坦なn型GaN連続膜
半導体層803が形成された。
Next, HV is applied on the sapphire substrate 800.
The n-type GaN continuous film semiconductor layer 803 is 300
It is grown to a thickness of μm. At this time, the n-type GaN continuous film semiconductor layer 803 grown by the HVPE process begins to grow from the portion where the sapphire substrate 800 is exposed, but as the thickness increases, the selective growth mask 80 made of SiO 2 is formed.
2 Growing to the left and right as if overhanging, eventually reaching 20
The selective growth mask 802 made of SiO 2 having a width of μm was covered. Thus, the n-type GaN continuous film semiconductor layer 803 having a flat surface was formed.

【0005】次に、このサファイア基板800上にn型
GaN連続膜半導体層803が形成されたウェハーに、
有機金属気相成長法(MOCVD法)によりn−GaN
クラッド層804、InGaN活性層805、p−Ga
Nコンタクト層806が形成された。以上までに作製さ
れた工程断面図を図8(b)に示す。
Next, a wafer in which an n-type GaN continuous film semiconductor layer 803 is formed on the sapphire substrate 800 is:
N-GaN by metal organic chemical vapor deposition (MOCVD)
Cladding layer 804, InGaN active layer 805, p-Ga
An N contact layer 806 was formed. FIG. 8B shows a cross-sectional view of the process manufactured as described above.

【0006】次に、図9の(a)従来例のLEDの上面
構造図と(b)従来例LEDのA−A’断面図に示すよ
うに、300μm角の発光領域810を残し、その回り
を取り囲むように通常のフォトリソグラフィー技術とド
ライエッチング技術を用いてp−GaNコンタクト層8
06、InGaN活性層805、n−GaNクラッド層
804を貫通するように除去し、n型GaN連続膜半導
体層803を露出させた。最後に、n型GaN連続膜半
導体層803の表面にn型電極807を、300μm角
のp−GaNコンタクト層806の表面に光透過性を有
するp型電極808をそれぞれ形成した。このようにし
て、作製したウェハーから、発光領域810の周辺でス
クライブし、個々のLEDを切り出し素子とした。この
ようにして作製する従来例のLEDが報告されている。
Next, as shown in FIG. 9A, which is a top view of a conventional LED, and FIG. 9B is a cross-sectional view taken along line AA ′ of the conventional LED, a light emitting region 810 of 300 μm square is left. The p-GaN contact layer 8 is formed to surround the p-GaN contact layer 8 by using a usual photolithography technique and a dry etching technique.
06, the InGaN active layer 805, and the n-GaN cladding layer 804 were removed so as to penetrate them, exposing the n-type GaN continuous film semiconductor layer 803. Finally, an n-type electrode 807 was formed on the surface of the n-type GaN continuous film semiconductor layer 803, and a light-transmissive p-type electrode 808 was formed on the surface of a 300 μm square p-GaN contact layer 806. A scribing was performed around the light emitting region 810 from the wafer thus manufactured, and individual LEDs were cut out to be used as elements. A conventional LED manufactured in this manner has been reported.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、このよ
うにして作製したLEDの特性を当該発明者が試験した
結果、20mAの電流を注入した場合の発光効率(電子
の光子への変換効率)が個々の素子により0.3%から
10%と大きく異なり、所望の5%以上の発光効率が得
られる歩留まりが2%と非常に低いことや、80℃の条
件下での約100時間の初期信頼性試験にて全ての素子
の発光効率が試験開始時の約30%以下に激減すること
が新たに判明した。
However, as a result of testing the characteristics of the LED fabricated in this way by the inventor, the luminous efficiency (the conversion efficiency of electrons into photons) when a current of 20 mA is injected is different. Varies greatly from 0.3% to 10% depending on the device, and the yield at which a desired luminous efficiency of 5% or more can be obtained is as low as 2%, and the initial reliability of about 100 hours at 80 ° C. In the test, it was newly found that the luminous efficiency of all the devices was drastically reduced to about 30% or less at the start of the test.

【0008】これらの従来素子の不良について、当該発
明者が詳細な検討を行った結果、下記のような事実が判
明した。 (1)選択成長マスク802の存在する選択成長マスク
直上領域811に位置するInGaN活性層805部分
での発光が非常に小さい。また、この発光効率の低下は
チップの発光領域810の周辺領域より発光領域810
の中央領域に選択成長マスク直上領域811が位置する
場合に特に顕著になることも分かった。これにより、選
択成長マスク直上領域811が発光領域810のどの部
分に位置しているかにより、大きく発光効率が変化す
る。 (2)上記の信頼性不良の素子においても、100時間
の信頼性試験走行後では、選択成長マスク直上領域81
1(幅20μm)のInGaN活性層805はその近傍
の両側約30μmを含め、合計80μmの領域で発光が
ほとんど認められない。
As a result of a detailed study by the inventor of these conventional elements, the following facts were found. (1) Light emission at the InGaN active layer 805 located in the region 811 immediately above the selective growth mask 802 where the selective growth mask 802 exists is extremely small. Also, this decrease in luminous efficiency is due to the fact that the light emitting region
It has also been found that this is particularly remarkable when the region 811 immediately above the selective growth mask is located in the central region of. As a result, the luminous efficiency greatly changes depending on the position of the region 811 immediately above the selective growth mask in the light emitting region 810. (2) Even in the case of the above-described device having poor reliability, the region 81 immediately above the selective growth mask after the reliability test run for 100 hours.
In the InGaN active layer 805 having a width of 1 (20 μm), almost no light emission is observed in a region of a total of 80 μm including about 30 μm on both sides in the vicinity thereof.

【0009】さらに従来例素子の結晶解析を行った結
果、選択成長マスク直上領域811に位置するInGa
N活性層805には、厚さ300μmのn型GaN連続
膜半導体層803を貫通して結晶転移が集中して導入さ
れていることが明確になった。図10にInGaN活性
層805における結晶転移の密度を、選択成長マスク8
02端からの距離をパラメータとして測定した結果を示
す。幅20μmの選択成長マスク直上領域811のIn
GaN活性層805には密度1012cm-2の結晶転移が
集中しており、さらに選択成長マスク802の端から1
0μm離れた位置でも1011cm-2の転移が観測され
た。選択成長マスク802の端から離れるにつれて結晶
転移は減少し、30μm以上離れた場所のInGaN活
性層805では結晶転移は107〜108cm-3にまで減
少した。このような傾向は、上記のように作製されたウ
ェハーのいずれの部分でも観測された。
Further, as a result of crystal analysis of the conventional device, InGa located in the region 811 immediately above the selective growth mask was obtained.
It became clear that crystal transition was concentrated and introduced into the N active layer 805 through the n-type GaN continuous film semiconductor layer 803 having a thickness of 300 μm. FIG. 10 shows the density of crystal transition in the InGaN active layer 805 by using the selective growth mask 8.
The result of measurement using the distance from the 02 end as a parameter is shown. In of the region 811 immediately above the selective growth mask having a width of 20 μm
Crystal transitions having a density of 10 12 cm −2 are concentrated in the GaN active layer 805, and furthermore, 1 mm from the edge of the selective growth mask 802.
A transition of 10 11 cm -2 was observed even at a position separated by 0 µm. As the distance from the edge of the selective growth mask 802 increases, the crystal transition decreases, and in the InGaN active layer 805 located at a distance of 30 μm or more, the crystal transition decreases to 10 7 to 10 8 cm −3 . Such a tendency was observed in any part of the wafer prepared as described above.

【0010】また、同様な方法により半導体レーザを上
述のようなn型GaN連続膜半導体層803上に、発光
領域に選択成長マスク直上領域811が含まれ、発振閾
値電流が700mAと大きく、かつ素子寿命も室温にお
いて1秒程度と非常に短かった。
In the same manner, a semiconductor laser is formed on the n-type GaN continuous film semiconductor layer 803 as described above by including a region 811 immediately above a selective growth mask in a light emitting region, having a large oscillation threshold current of 700 mA, and The life was very short at room temperature, about 1 second.

【0011】上記のように、従来技術においては、下記
のような問題点が明らかになった。 (1)選択成長法を用いて作製した連続膜半導体層上の
発光素子において、選択成長マスク直上領域811にお
いて発光効率の低下が見られるため、発光領域に選択成
長マスク直上領域が含まれるチップでは劇的に発光効率
が低下する。 (2)GaN連続膜の上に形成した半導体レーザ素子の
寿命が短く、半導体レーザ素子は得られなかった。
As described above, the following problems have been clarified in the prior art. (1) In a light-emitting element on a continuous film semiconductor layer manufactured by using the selective growth method, a decrease in luminous efficiency is observed in a region 811 immediately above the selective growth mask. The luminous efficiency drops dramatically. (2) The life of the semiconductor laser device formed on the continuous GaN film was short, and no semiconductor laser device was obtained.

【0012】このため、基板上に、基板と異なる格子定
数や熱膨張係数を有する連続膜半導体層を成長させ、そ
の上に形成する半導体発光素子に、格子定数差や熱膨張
係数差から引き起こされる発光効率の低下や信頼性不良
を防止することは不可能であった。
For this reason, a continuous film semiconductor layer having a lattice constant and a thermal expansion coefficient different from those of the substrate is grown on the substrate, and a semiconductor light emitting element formed thereon is caused by the lattice constant difference and the thermal expansion coefficient difference. It has not been possible to prevent a decrease in luminous efficiency or poor reliability.

【0013】従って、部分的成長抑制構造を利用して、
基板と格子定数または熱膨張係数が異なる連続膜半導体
層を形成した上に、さらに半導体発光素子を形成する場
合における発光効率の低下および信頼性の悪化を防止す
ることを目的とする。
Therefore, utilizing the partial growth suppressing structure,
It is an object of the present invention to prevent a decrease in luminous efficiency and a decrease in reliability when a semiconductor light emitting element is further formed after a continuous film semiconductor layer having a lattice constant or a thermal expansion coefficient different from that of a substrate is formed.

【0014】[0014]

【課題を解決するための手段】本発明の請求項1は、成
長抑制構造上への結晶成長により得られる成長抑制構造
直上領域を含む連続膜半導体層と、光を発生させる活性
層とを有する半導体発光素子であって、該活性層の内、
電流注入により光を発生する発光領域が前記成長抑制構
造直上領域以外の領域に形成されていることにより構成
されている。
A first aspect of the present invention has a continuous film semiconductor layer including a region immediately above a growth suppression structure obtained by crystal growth on a growth suppression structure, and an active layer for generating light. A semiconductor light emitting device, wherein:
The light emitting region that generates light by current injection is formed in a region other than the region immediately above the growth suppressing structure.

【0015】本発明における請求項2は、前記発光領域
は成長抑制構造直上領域から30μm以上離れた位置に
形成されていることにより構成され、さらに請求項3は
前記発光領域と前記成長抑制構造直上領域との間の領域
では、前記活性層が除去されていることにより構成され
ている。
According to a second aspect of the present invention, the light emitting region is formed at a position at least 30 μm away from the region immediately above the growth suppressing structure. The region between the regions is formed by removing the active layer.

【0016】一方、請求項4は、基板上に成長抑制構造
を形成する第1工程と、前記基板および前記成長抑制構
造の両方を連続して覆うように前記基板と格子定数また
は熱膨張係数が異なる連続膜半導体層を形成する第2工
程と、前記連続膜半導体層の上に光を発生させる活性層
を含む多層構造体を形成する第3工程と、前記成長抑制
構造部の直上領域を除いて前記活性層における発光領域
を規定するための構造を形成する第4工程と、を有する
ことにより構成されており、さらに請求項5は、半導体
発光素子をウェハーから複数個の半導体発光素子に分割
する工程を有する半導体発光素子の製造方法であって、
前記第4工程後、前記成長抑制構造直上の前記活性層が
半導体発光素子に含まれないように半導体発光素子をウ
ェハーから分割する第5工程とを含むことにより構成さ
れ、請求項6は、前記第5工程において、前記成長抑制
構造直上の端から30μm以内の領域に残存する前記活
性層が、半導体発光素子に含まれないように半導体発光
素子を分割することにより構成されている。
On the other hand, a fourth step is to form a growth suppressing structure on the substrate, and the substrate and the lattice constant or the thermal expansion coefficient are so set as to continuously cover both the substrate and the growth suppressing structure. A second step of forming a different continuous film semiconductor layer, a third step of forming a multilayer structure including an active layer for generating light on the continuous film semiconductor layer, and excluding a region immediately above the growth suppressing structure portion And a fourth step of forming a structure for defining a light emitting region in the active layer by dividing the semiconductor light emitting element from a wafer into a plurality of semiconductor light emitting elements. A method for manufacturing a semiconductor light emitting device having a step of
A fifth step of dividing the semiconductor light emitting device from the wafer so that the active layer immediately above the growth suppressing structure is not included in the semiconductor light emitting device after the fourth step. In the fifth step, the semiconductor light emitting device is divided so that the active layer remaining in a region within 30 μm from the end immediately above the growth suppressing structure is not included in the semiconductor light emitting device.

【0017】[0017]

【発明の実施の形態】以下に本発明を実施した例を用い
て説明する。 (実施の形態1)図1に本発明を実施した半導体レーザ
素子の一例を示す。本半導体レーザ素子は、n−GaN
連続膜半導体層102、n−GaNバッファ層103、
n−Al0.1Ga0.9Nクラッド層104、多重量子井戸
活性層105、p−Al0.1Ga0.9Nクラッド層10
6、p−GaNコンタクト層107から構成されてお
り、リッジ導波路としてレーザの発光領域を規定するた
めのメサストライプ110、さらには、電流注入用のp
型電極111、n型電極112から構成されている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described with reference to embodiments. Embodiment 1 FIG. 1 shows an example of a semiconductor laser device embodying the present invention. This semiconductor laser device is n-GaN
Continuous film semiconductor layer 102, n-GaN buffer layer 103,
n-Al 0.1 Ga 0.9 N cladding layer 104, multiple quantum well active layer 105, p-Al 0.1 Ga 0.9 N cladding layer 10
6, a p-GaN contact layer 107, a mesa stripe 110 for defining a laser emission region as a ridge waveguide, and a p-type current injection p.
It comprises a mold electrode 111 and an n-type electrode 112.

【0018】次に、図2を用いて本実施例素子の作製工
程を説明する。まず、サファイア基板100の上にMO
CVD法によりGaNバッファ層101を1μm厚成長
させる。次に、GaNバッファ層101の表面上に通常
のスパッタ法によりSiO2膜を0.4μm厚形成させ
た後、通常のフォトリソグラフィ技術とエッチング技術
により幅10μmでピッチ150μmの周期的SiO2
からなる選択成長マスク150と幅10μmでピッチ5
00μmの周期的SiO2からなる選択成長マスク15
1とが互いに直交する形状に形成した。以上までに作製
された半導体レーザ素子の工程断面図を図2(a)に示
す。
Next, a manufacturing process of the device of this embodiment will be described with reference to FIG. First, the MO was placed on the sapphire substrate 100.
The GaN buffer layer 101 is grown to a thickness of 1 μm by the CVD method. Then, after a SiO 2 film was 0.4μm thick formed by conventional sputtering method on the surface of the GaN buffer layer 101, typically photo-periodic SiO 2 pitch 150μm in width 10μm by lithography and etching techniques
Selective growth mask 150 made of
Selective growth mask 15 made of 00 μm periodic SiO 2
1 and 2 were formed in a shape orthogonal to each other. FIG. 2A is a process sectional view of the semiconductor laser device manufactured as described above.

【0019】続いて、このウェハー上にHVPE法によ
り、n−GaN連続膜半導体層102を150μm厚成
長させた。基板温度は1020℃として35分の成長に
より150μm厚の成長が完了した。この成長時、選択
成長マスク150、151が成長抑制構造として働くた
め、従来例にて説明のように、成長初期にはGaNバッ
ファ膜101が露出した領域でのみ成長は起こり、次第
に、選択成長マスク150、151上に横方向に成長が
進み、最終的に150μm厚の成長が終了した段階で
は、n−GaN連続膜半導体層102は連続膜を呈して
おり、その表面はスムースになった。
Subsequently, an n-GaN continuous film semiconductor layer 102 was grown on this wafer by HVPE to a thickness of 150 μm. With the substrate temperature set to 1020 ° C., the growth of 150 μm thickness was completed by the growth for 35 minutes. During this growth, since the selective growth masks 150 and 151 function as a growth suppressing structure, growth occurs only in the region where the GaN buffer film 101 is exposed at the beginning of growth, as described in the conventional example, and gradually the selective growth mask At the stage where the growth progressed in the lateral direction on 150 and 151, and finally the growth of 150 μm in thickness was completed, the n-GaN continuous film semiconductor layer 102 was a continuous film, and the surface was smooth.

【0020】次に、引き続きMOCVD法により、この
n−GaN連続膜半導体層102の上に、n−GaNバ
ッファ層103を0.5μm厚、n−Al0.1Ga0.9
クラッド層104を0.2μm厚、4nm厚のIn0.25
Ga0.75N井戸層2層と3nm厚のIn0.05Ga0.95
バリア層3層からなる多重量子井戸活性層105、p−
Al0.1Ga0.9Nクラッド層106を0.2μm厚、p
−GaNコンタクト層107を0.7μm厚成長させ
た。以上までに作製された半導体レーザ素子の工程断面
図を図2(b)に示す。
Next, an n-GaN buffer layer 103 having a thickness of 0.5 μm and n-Al 0.1 Ga 0.9 N is continuously formed on the n-GaN continuous film semiconductor layer 102 by MOCVD.
The cladding layer 104 is made of 0.2 μm thick, 4 nm thick In 0.25
Two Ga 0.75 N well layers and 3 nm thick In 0.05 Ga 0.95 N
The multiple quantum well active layer 105 composed of three barrier layers, p-
The Al 0.1 Ga 0.9 N cladding layer 106 is 0.2 μm thick,
The GaN contact layer 107 was grown to a thickness of 0.7 μm. FIG. 2B is a process sectional view of the semiconductor laser device manufactured as described above.

【0021】続いて、幅2μm、高さ0.7μmのメサ
ストライプ110を選択成長マスク150の直上領域1
52以外の領域に選択成長マスク150とほぼ平行に形
成した。この時、メサストライプ110が素子の上方か
ら観察して隣り合う選択成長マスク150のほぼ中央に
位置するようにした。このメサストライプ110の形成
には通常のフォトリソグラフィ技術とドライエッチング
技術を適用した。この後、メサストライプ110を上面
にストライプ状のp型電極111を形成した後、ウェハ
ー裏面を研磨することによりウェハー厚さを約120μ
mとし(すなわち、サファイア基板100、GaNバッ
ファ層101、選択成長マスク150、151を完全に
除去し、n−GaN連続膜半導体層102がウェハー裏
面に露出するようにし)、n−GaN連続膜半導体層1
02の露出した裏面の全面にn型電極112を形成し
た。以上までに作製された半導体レーザ素子の工程断面
図を図2(c)に示す。
Subsequently, a mesa stripe 110 having a width of 2 μm and a height of 0.7 μm is formed in the region 1 directly above the selective growth mask 150.
A region other than 52 was formed substantially parallel to the selective growth mask 150. At this time, the mesa stripe 110 was positioned substantially at the center of the adjacent selective growth mask 150 as viewed from above the element. For the formation of the mesa stripe 110, ordinary photolithography technology and dry etching technology were applied. Thereafter, a stripe-shaped p-type electrode 111 is formed on the mesa stripe 110 on the upper surface, and the wafer thickness is reduced to about 120 μm by polishing the back surface of the wafer.
m (that is, the sapphire substrate 100, the GaN buffer layer 101, and the selective growth masks 150 and 151 are completely removed so that the n-GaN continuous film semiconductor layer 102 is exposed on the back surface of the wafer). Layer 1
The n-type electrode 112 was formed on the entire exposed back surface of the substrate 02. FIG. 2C is a process sectional view of the semiconductor laser device manufactured as described above.

【0022】次に、劈開によりレーザ共振器を構成する
ミラー面を形成した。この劈開工程は以下のようにして
実施した。まず、ウェハー裏面(すなわちn−GaN連
続膜層103側)の隅近傍の2箇所にけがき傷を入れ、
このけがき傷の位置において、選択成長マスク151を
形成した方向と平行方向に劈開してレーザ共振器ミラー
を形成した。この時、2箇所のけがき傷は互いに隣接す
る選択成長マスク151のエッジ部分から50μm離れ
た位置に形成し、選択成長マスク151の直上領域15
3がレーザ素子に含まれないようにした。従って、レー
ザ共振器長は400μmであった。最後に、選択成長マ
スク150の直上領域152の部分をスクライブし、個
々のレーザチップに分割した。以上の工程を経て図1に
示すレーザ素子が完成する。
Next, a mirror surface constituting a laser resonator was formed by cleavage. This cleavage step was performed as follows. First, two scratches were made near two corners of the back surface of the wafer (that is, the n-GaN continuous film layer 103 side).
The laser cavity mirror was formed by cleaving at the position of the scratch in a direction parallel to the direction in which the selective growth mask 151 was formed. At this time, the two scratches are formed at positions 50 μm away from the edge portions of the selective growth mask 151 adjacent to each other, and the area 15 directly above the selective growth mask 151 is formed.
3 was not included in the laser element. Therefore, the laser cavity length was 400 μm. Finally, the portion of the region 152 immediately above the selective growth mask 150 was scribed and divided into individual laser chips. Through the above steps, the laser device shown in FIG. 1 is completed.

【0023】以上のようにして作製したレーザ素子は、
閾値電流25mAでレーザ発振が実現できた。また、本
レーザ素子を50℃雰囲気、3mW出力の条件下におい
て信頼性試験を実施した結果、初期の50時間以内に故
障に至るレーザ素子を除いて、ほとんどの素子において
1000時間以上の寿命が確認でき、メディアン寿命
(試験した半分の素子が故障する時間)は1500時間
であった。この信頼性は当該素子を光ディスク用光源と
して利用する場合にでも十分な特性である。この信頼性
の改善は、本レーザ素子では、n−GaN連続膜半導体
層102を成長させるために形成した成長抑制構造であ
る選択成長マスク150、151上において結晶欠陥が
集中する直上領域152、153がレーザ素子の発光領
域(この場合は活性層105に電流が選択的に注入され
るメサストライプ110が形成されている部分)に含ま
れないように、選択成長マスク150、151の形状
と、選択成長マスク150に対するメサストライプ11
0の相対位置、および選択成長マスク151に対するレ
ーザ共振器ミラーの劈開のための相対位置を設定したこ
とによるものと理解できる。
The laser device manufactured as described above is
Laser oscillation was realized with a threshold current of 25 mA. In addition, as a result of performing a reliability test on the laser device under the conditions of 50 ° C. atmosphere and 3 mW output, it was confirmed that the life of most devices was 1000 hours or more, except for the laser device which failed within the initial 50 hours. The resulting median life (time during which half of the devices tested failed) was 1500 hours. This reliability is a sufficient characteristic even when the element is used as a light source for an optical disk. This improvement in reliability can be achieved by the present laser device by the regions 152, 153 directly above where crystal defects are concentrated on the selective growth masks 150, 151 which are growth suppression structures formed for growing the n-GaN continuous film semiconductor layer 102. Is not included in the light emitting region of the laser element (in this case, the portion where the mesa stripe 110 in which the current is selectively injected into the active layer 105 is formed). Mesa stripe 11 for growth mask 150
It can be understood that this is because the relative position of 0 and the relative position for cleavage of the laser resonator mirror with respect to the selective growth mask 151 are set.

【0024】上記の発明を実施したレーザ素子では、メ
サストライプ110を隣接する選択成長マスク150の
直上領域152同士の中央となるように(すなわち、選
択成長マスク150の端から70μm離れた部分に)形
成されている。上記の実施例素子と同様の構造で、メサ
ストライプ110の直上領域152(すなわち選択成長
マスク150)端からの距離を0μm(すなわち直上領
域152内にメサストライプ110を形成した場合)、
10μm、20μm、30μm、50μm、70μmと
変化させたレーザ素子を作製し、上記と同様の信頼性試
験を実施した。この時、素子分離ためのスクライブ位置
はいずれの素子においても隣接するメサストライプ11
0の中心付近とし、スクライブ位置のメサストライプ1
10との相対距離を一定とした。その結果を図3に示
す。横軸は直上領域152の中心からメサストライプ1
10までの距離、縦軸はメディアン寿命を示している。
この結果から、実用上必要とされる1000時間以上の
メディアン寿命を確保するためにはメサストライプ11
0を直上領域152から30μm以上離れた位置に形成
することが必要であることが分かった。
In the laser device embodying the present invention, the mesa stripe 110 is located at the center between the regions 152 immediately above the adjacent selective growth masks 150 (ie, at a portion 70 μm away from the edge of the selective growth mask 150). Is formed. With a structure similar to that of the above-described embodiment element, the distance from the end of the mesa stripe 110 directly above the region 152 (that is, the selective growth mask 150) is 0 μm (that is, when the mesa stripe 110 is formed in the region 152 directly above),
Laser elements were manufactured in the conditions of 10 μm, 20 μm, 30 μm, 50 μm, and 70 μm, and the same reliability test as described above was performed. At this time, the scribe position for element isolation is set to the adjacent mesa stripe 11 in any element.
Mesa stripe 1 at the scribe position near the center of 0
The relative distance to the position 10 was constant. The result is shown in FIG. The horizontal axis is the mesa stripe 1 from the center of the area 152 immediately above.
The distance up to 10 and the vertical axis indicate the median life.
From this result, in order to secure a median life of 1000 hours or more required for practical use, the mesa stripe 11
It was found that it was necessary to form 0 at a position 30 μm or more away from the region 152 immediately above.

【0025】(実施の形態2)次に、本発明を発光ダイ
オードに適用した場合について述べる。図4に第2の実
施形態素子の構造図を示す。n−GaN連続膜半導体層
401、n−GaNバッファ層402、In0.1Ga0.9
N歪み緩和層403、In0.5Ga0.5N単一量子井戸活
性層404、p−Al0.2Ga0.8N蒸発防止層405、
p−GaNコンタクト層406、およびn型電極40
7、p型電極408から構成されている。また本実施例
の素子ではメサ410により発光領域が規定されてい
る。
(Embodiment 2) Next, a case where the present invention is applied to a light emitting diode will be described. FIG. 4 shows a structural view of the device according to the second embodiment. n-GaN continuous film semiconductor layer 401, n-GaN buffer layer 402, In 0.1 Ga 0.9
N strain relaxation layer 403, In 0.5 Ga 0.5 N single quantum well active layer 404, p-Al 0.2 Ga 0.8 N evaporation preventing layer 405,
p-GaN contact layer 406 and n-type electrode 40
7. It is composed of a p-type electrode 408. In the device of this embodiment, the light emitting region is defined by the mesa 410.

【0026】次に、本発光素子の作製方法について説明
する。まず、サファイア基板400表面にダイシングに
より幅40μm、深さ50μmの溝構造450を400
μmピッチで格子状に形成する。以上までに作製された
半導体素子の工程断面図を図5(a)に示す。
Next, a method of manufacturing the present light emitting device will be described. First, a groove structure 450 having a width of 40 μm and a depth of 50 μm is formed on the surface of the sapphire substrate 400 by dicing.
It is formed in a grid at a pitch of μm. FIG. 5A is a process sectional view of the semiconductor device manufactured as described above.

【0027】次にHVPE法により、厚さ300μmの
n−GaN連続膜半導体層401を成長させる。この
時、サファイア基板400に形成した溝構造450があ
るため成長初期においてn−GaN連続膜半導体層40
1は平坦な面としての成長ができないが、成長層厚を増
すに従って徐々に左右の壁からの成長により溝構造45
0を埋まり、表面の溝は平坦に埋め込まれることとなっ
た。すなわち、実効的に溝450での成長が遅いのと同
様の効果を実現でき、300μmの成長終了時にはn−
GaN連続膜層401は、連続した表面が平坦な単一の
層にすることができた。
Next, an n-GaN continuous film semiconductor layer 401 having a thickness of 300 μm is grown by HVPE. At this time, since the groove structure 450 is formed in the sapphire substrate 400, the n-GaN continuous film semiconductor layer 40 is initially formed.
1 cannot grow as a flat surface, but as the growth layer thickness increases, the groove structure 45 gradually grows from the left and right walls.
0 was buried, and the groove on the surface was buried flat. That is, the same effect as the slow growth in the trench 450 can be realized effectively, and at the end of the growth of 300 μm, n−
The continuous GaN film layer 401 could be a single continuous layer having a flat surface.

【0028】次に、分子線エピタキシアル法(MBE
法)により、n−GaN連続膜半導体層401上にn−
GaNバッファ層402を0.4μm厚、In0.2Ga
0.8N歪み緩和層403を0.05μm厚、In0.45
0.55N単一量子井戸活性層404を4nm厚、p−A
0.1Ga0.9N蒸発防止層405を0.1μm厚、p−
GaNコンタクト層406を0.4μm厚成長させた。
以上までに作製された発光素子の工程断面図を図5
(b)に示す。
Next, the molecular beam epitaxy method (MBE
N) on the n-GaN continuous film semiconductor layer 401
0.4μm thickness of GaN buffer layer 402, an In 0.2 Ga
0.8 N strain relaxation layer 403 with a thickness of 0.05 μm, In 0.45 G
a 0.55 N single quantum well active layer 404 is 4 nm thick, p-A
l 0.1 Ga 0.9 N evaporation preventing layer 405 is 0.1 μm thick, p-
The GaN contact layer 406 was grown to a thickness of 0.4 μm.
FIG. 5 is a process sectional view of the light emitting device manufactured up to this point.
(B).

【0029】さらに、通常のフォトリソグラフィ技術と
ドライエッチング技術を用いてIn0.45Ga0.55N単一
量子井戸活性層404を含む300μm角メサ410を
周期的に残し、その間の領域を100μm幅でエッチン
グし、n−GaN連続膜半導体層401をエッチング底
面に露出させた。すなわち、エッチングを行った領域は
400μmピッチの格子状の形状となり、これにより、
溝構造450の上にMBE成長された欠陥を多く含む溝
構造450の直上領域451とその周辺に含まれるIn
0.45Ga0.55N単一量子井戸活性層404を完全に除去
した。本実施の形態では溝構造450が成長抑制構造と
なる。以上までに作製された発光素子の工程断面図を図
5(c)に示す。
Further, a 300 μm square mesa 410 including an In 0.45 Ga 0.55 N single quantum well active layer 404 is periodically left using a normal photolithography technique and a dry etching technique, and a region therebetween is etched with a width of 100 μm. Then, the n-GaN continuous film semiconductor layer 401 was exposed on the etching bottom surface. That is, the etched region has a lattice shape with a pitch of 400 μm,
A region 451 immediately above the trench structure 450 containing many defects grown by MBE on the trench structure 450 and In contained in the periphery thereof.
The 0.45 Ga 0.55 N single quantum well active layer 404 was completely removed. In this embodiment, the groove structure 450 is a growth suppressing structure. FIG. 5C is a process sectional view of the light-emitting element manufactured as described above.

【0030】次に、ウェハーの裏面を研磨し、サファイ
ア基板400を完全に除去しn−GaN連続膜半導体層
401をウェハー裏面に露出させた後、このn−GaN
連続膜半導体層401にn型電極407を、メサ410
の表面に光透過性のp型電極408を形成した。最後
に、溝構造450の直上領域451でスクライブするこ
とにより、個々の発光ダイオードチップとした。以上ま
でに作製された発光素子の工程断面図を図4に示す。
Next, the back surface of the wafer is polished, the sapphire substrate 400 is completely removed, and the n-GaN continuous film semiconductor layer 401 is exposed on the back surface of the wafer.
An n-type electrode 407 is formed on the continuous film semiconductor layer 401,
A light transmissive p-type electrode 408 was formed on the surface of. Finally, individual light emitting diode chips were obtained by scribing in the region 451 immediately above the groove structure 450. FIG. 4 is a process cross-sectional view of the light-emitting element manufactured as described above.

【0031】このようにして作製された発光ダイオード
の電子の光子への変換効率を測定したことろ、実用上問
題がないとみなすことが出来る変換効率5%以上の素子
の歩留まりが85%と高かった。さらに、本実施例素子
を従来例素子と同様の条件にて信頼性試験を実施したと
ころ、1000時間経過後においても、試験開始時の9
5〜103%の発光強度を得ることができ、実用上問題
のない信頼性が確保された。
When the conversion efficiency of electrons to photons of the light emitting diode thus manufactured was measured, the yield of devices having a conversion efficiency of 5% or more, which can be regarded as having no practical problem, was as high as 85%. Was. Further, a reliability test was performed on the device of this example under the same conditions as those of the device of the related art.
A luminescence intensity of 5 to 103% was obtained, and reliability without practical problems was secured.

【0032】本実施形態の発光素子における発光領域
は、In0.45Ga0.55N単一量子井戸活性層404が残
存しているメサ410部に相当する。n−GaN連続膜
半導体層401成長時に成長抑制構造として利用した溝
構造450の直上領域451を除いた領域にメサ410
が形成されているため、作製された全ての発光素子にお
いて発光領域には溝構造450の直上領域451は含ま
れていない。また、エッチングによりIn0.45Ga0.55
N単一量子井戸活性層404が除去された幅は100μ
mであり、メサ410部の発光領域は幅40μmの溝構
造450の端から30μm離れたところに形成されてい
ることとなる。上記のように発光効率の高い素子を歩留
まり良く得ることができ、かつ問題のない信頼性を実現
できるのは、HVPE法およびMOCVD法による結晶
成長工程により溝構造450の直上領域451に集中的
に導入された結晶欠陥の影響が、In0.45Ga0.55N単
一量子井戸活性層404での発光に悪影響を与えず、比
較的結晶欠陥の少ない部分に制御性良く発光領域を配置
することが可能となったためと考えられる。
The light emitting region in the light emitting device of this embodiment corresponds to the mesa 410 where the In 0.45 Ga 0.55 N single quantum well active layer 404 remains. A mesa 410 is formed in a region excluding a region 451 immediately above a trench structure 450 used as a growth suppressing structure when growing the n-GaN continuous film semiconductor layer 401.
Is formed, the light-emitting region does not include the region 451 immediately above the groove structure 450 in all of the manufactured light-emitting elements. Further, by etching, In 0.45 Ga 0.55
The width from which the N single quantum well active layer 404 is removed is 100 μm.
m, and the light emitting region of the mesa 410 is formed at a distance of 30 μm from the end of the groove structure 450 having a width of 40 μm. As described above, an element having high luminous efficiency can be obtained with good yield and reliability without any problem can be realized because the crystal growth process by the HVPE method and the MOCVD method concentrates on the region 451 directly above the groove structure 450. The effect of the introduced crystal defects does not adversely affect the light emission in the In 0.45 Ga 0.55 N single quantum well active layer 404, and the light emitting region can be arranged with good controllability in a portion having relatively few crystal defects. It is thought that it became.

【0033】なお、上記の実施形態の発光素子におい
て、発光素子作製工程および構造はほぼ同等とし、溝構
造450のピッチのみを上記の例の400μmから50
0μmおよび300μmに変化させた場合の発光素子を
試作した。この場合においてもメサ410の大きさや作
製ピッチはそれぞれ300μm、400μmと上記の実
施形態素子のままとした。これらの発光素子の発光特性
を測定したところ、溝450のピッチを300μmと小
さくした素子では、5%以上の発光効率が得られる歩留
まりは16%と激減した。一方、500μmと広げた発
光素子では38%であった。これは、溝構造450のピ
ッチが、個々の発光ダイオードを形成するメサ410の
作製ピッチと同一であることが重要であることを示して
いる。従って、同一面積のウェハーからより多くの発光
素子を作製するためには、全ての発光素子において溝構
造の直上領域451が発光領域に含有されないようにす
べきである。この意味に置いて、溝構造450のピッチ
をメサ410作製ピッチの整数倍にしても良いことは言
うまでもない。
In the light emitting device of the above embodiment, the light emitting device manufacturing process and the structure are almost the same, and only the pitch of the groove structure 450 is changed from 400 μm of the above example to 50 μm.
Light emitting devices were manufactured on a trial basis when the thickness was changed to 0 μm and 300 μm. Also in this case, the size and the manufacturing pitch of the mesa 410 were 300 μm and 400 μm, respectively, which were the same as those of the above-described embodiment. When the light-emitting characteristics of these light-emitting elements were measured, the yield at which luminous efficiency of 5% or more was obtained was reduced to 16% in the element in which the pitch of the grooves 450 was reduced to 300 μm. On the other hand, it was 38% for the light emitting element expanded to 500 μm. This indicates that it is important that the pitch of the groove structure 450 is the same as the production pitch of the mesas 410 forming the individual light emitting diodes. Therefore, in order to manufacture more light emitting elements from a wafer having the same area, the region 451 immediately above the groove structure should not be included in the light emitting area in all the light emitting elements. In this sense, it goes without saying that the pitch of the groove structure 450 may be an integral multiple of the pitch of the mesa 410.

【0034】(実施形態3)次に、成長抑制構造自体を
レーザ素子に残存させた実施形態について説明する。図
6に本実施形態の素子構造図を示す。本実施形態の素子
構造はn−SiC基板600と、GaNバッファ層60
1、n−GaN連続膜半導体層602、n−GaNバッ
ファ層603、n−Al0.1Ga0.9Nクラッド層60
4、3nm厚のIn0.1Ga0.85Al0.05Nバリア層3
層と3nm厚のIn0.2Ga0.8N量子井戸層2層からな
る多重量子井戸活性層605、p−Al0.1Ga0.9Nク
ラッド層606、p−GaNコンタクト層607、から
なる半導体層構造と、p型電極611、n型電極61
2、さらには、導波路と電流通路を規定するメサストラ
イプ610、共振器ミラーとなるエッチドミラー613
を有している。
(Embodiment 3) Next, an embodiment in which the growth suppressing structure itself is left in the laser device will be described. FIG. 6 shows an element structure diagram of the present embodiment. The device structure of the present embodiment includes an n-SiC substrate 600 and a GaN buffer layer 60.
1. n-GaN continuous film semiconductor layer 602, n-GaN buffer layer 603, n-Al 0.1 Ga 0.9 N cladding layer 60
4, 3 nm thick In 0.1 Ga 0.85 Al 0.05 N barrier layer 3
A multi-quantum well active layer 605 composed of two layers of In 0.2 Ga 0.8 N quantum well layers having a thickness of 3 nm, a p-Al 0.1 Ga 0.9 N cladding layer 606, and a p-GaN contact layer 607; Type electrode 611, n-type electrode 61
2. Further, a mesa stripe 610 for defining a waveguide and a current path, and an etched mirror 613 serving as a resonator mirror
have.

【0035】以下に、本実施形態のレーザ素子の作製方
法について説明する。(工程図は図2と類似しているの
でここでは省略する。)まず、n−SiC基板600上
に、SiNxからなる幅10μmで周期が100μmの
選択成長マスク650と、幅が10μmで周期が400
μmの選択成長マスク651とが互いに直交するように
形成した。このウェハー上にMOCVD法によりGaN
バッファ層601を30nm厚、n−GaN連続膜半導
体層602を100μm厚、n−GaNバッファ層60
3を0.1μm、n−AlGaNクラッド層604を
0.3μm厚、多重量子井戸活性層605、p−AlG
aNクラッド層606を0.3μm厚、p−GaNコン
タクト層607を1.0μm厚連続的に結晶成長させ
る。この時、n−GaN連続膜半導体層602の成長に
おいては、厚さが30μm以下の状態では選択成長マス
ク650、651上では未成長部分が残存しており、結
晶は連続した膜を呈していなかったが、さらに成長を続
けて厚さが100μmに達した段階では、n−GaN連
続膜半導体層602表面は実施形態1と同様に平坦で連
続した単膜を呈しており、その上に連続的に形成された
積層構造に含まれる各層603〜607もまた平坦な層
として成長された。
Hereinafter, a method for fabricating the laser device of this embodiment will be described. (Process drawing is omitted here because it is similar to FIG. 2.) First, the period over n-SiC substrate 600, a selective growth mask 650 period of 100μm in width 10μm consisting of SiN x, a width of 10μm Is 400
The μm selective growth masks 651 were formed so as to be orthogonal to each other. GaN is deposited on this wafer by MOCVD.
The buffer layer 601 has a thickness of 30 nm, the n-GaN continuous film semiconductor layer 602 has a thickness of 100 μm, and the n-GaN buffer layer 60 has a thickness of 100 μm.
3 is 0.1 μm, the n-AlGaN cladding layer 604 is 0.3 μm thick, the multiple quantum well active layer 605, p-AlG
The aN cladding layer 606 and the p-GaN contact layer 607 are continuously grown with a thickness of 0.3 μm and a thickness of 1.0 μm, respectively. At this time, in the growth of the n-GaN continuous film semiconductor layer 602, when the thickness is 30 μm or less, an ungrown portion remains on the selective growth masks 650 and 651, and the crystal does not exhibit a continuous film. However, at the stage where the growth is further continued and the thickness reaches 100 μm, the surface of the n-GaN continuous film semiconductor layer 602 exhibits a flat and continuous single film as in the first embodiment, and the continuous Each of the layers 603 to 607 included in the stacked structure formed as described above was also grown as a flat layer.

【0036】次に、通常のフォトリソグラフィ技術とエ
ッチング技術を利用し、高さ0.8μm、幅2μmのメ
サストライプ610を選択成長マスク651と平行に形
成した。このメサストライプ610はレーザ導波路を活
性層605に形成するばかりでなく、活性層605に注
入される電流の通路もメサストライプ610直下近傍部
分に規定し、効率よく電子をレーザ光に変換する働きを
する。本工程において、メサストライプ610は、両側
の選択成長マスク651の直上領域653の中央、すな
わち選択成長マスク651の端とメサストライプ610
の端の間隔が39μmとなるように形成した。
Next, a mesa stripe 610 having a height of 0.8 μm and a width of 2 μm was formed in parallel with the selective growth mask 651 by using ordinary photolithography and etching techniques. The mesa stripe 610 not only forms a laser waveguide in the active layer 605, but also regulates the path of a current injected into the active layer 605 in a portion immediately below the mesa stripe 610, thereby efficiently converting electrons into laser light. do. In this step, the mesa stripe 610 is formed at the center of the region 653 immediately above the selective growth mask 651 on both sides, that is, the end of the selective growth mask 651 and the mesa stripe 610.
Was formed so that the distance between the ends of the pattern was 39 μm.

【0037】次に、通常のエッチドミラー形成のための
フォトリソグラフィ技術とドライエッチング技術を利用
し、レーザ共振器ミラーとなるエッチドミラー613を
形成した。この時、エッチドミラー613が選択成長マ
スク650に平行であり、かつ選択成長マスク650の
直上領域652の活性層605をエッチングより除去す
るように、選択成長マスク650の直上領域652を中
心として全幅100μmの領域にエッチングを施し、n
−GaN連続膜半導体層602がエッチング底面に露出
するまでエッチングを行った。この工程によりレーザ共
振器となるべき一組の共振器ミラーが形成され、本実施
形態のレーザ素子における共振器長は300μmとし
た。すなわち、選択成長マスク650の周期と同じ40
0μm周期でエッチドミラー形成のためのエッチングを
実施したことになる。
Next, an etched mirror 613 serving as a laser resonator mirror was formed by using a photolithography technique and a dry etching technique for forming an ordinary etched mirror. At this time, the etched mirror 613 is parallel to the selective growth mask 650 and the entire width centering on the region 652 immediately above the selective growth mask 650 is centered so that the active layer 605 in the region 652 immediately above the selective growth mask 650 is removed by etching. Etching is performed on a 100 μm area, and n
The etching was performed until the -GaN continuous film semiconductor layer 602 was exposed on the etching bottom surface. By this step, a set of cavity mirrors to be a laser cavity was formed, and the cavity length of the laser device of the present embodiment was 300 μm. That is, 40, which is the same as the cycle of the selective growth mask 650,
This means that etching for forming an etched mirror was performed at a period of 0 μm.

【0038】最後に、メサストライプ610上面にp型
電極611を、n−SiC基板600裏面全面にn型電
極612を形成した後、選択成長マスク650、651
の直上領域652、653の部分でスクライブすること
により個々のレーザ素子に分割した。
Finally, after forming a p-type electrode 611 on the upper surface of the mesa stripe 610 and an n-type electrode 612 on the entire back surface of the n-SiC substrate 600, selective growth masks 650 and 651 are formed.
Are divided into individual laser elements by scribing in the areas 652 and 653 immediately above the laser elements.

【0039】本実施形態のレーザ素子を実施形態2の6
0℃雰囲気下、5mW光出力の条件下での信頼性試験を
実施したところ、初期24時間の異常劣化を示した素子
を除いて、全て1000時間以上の寿命を有することが
確認できた。この場合のメディアン寿命は約1600時
間であった。このように、信頼性の高いレーザが実現で
きたのは、選択成長マスク650の直上領域652が発
光領域であるメサストライプ610に全く含まれず、レ
ーザ素子の劣化を引き起こす結晶欠陥が少ない領域のみ
の活性層605が発光に寄与している効果と推察され
る。
The laser device of the present embodiment is replaced with the laser device of the second embodiment 6
A reliability test was performed under an atmosphere of 0 ° C. and a light output of 5 mW. As a result, it was confirmed that all the devices had a lifetime of 1,000 hours or more, except for the devices that showed abnormal deterioration for the first 24 hours. The median life in this case was about 1600 hours. As described above, a highly reliable laser can be realized only in a region where the region 652 directly above the selective growth mask 650 is not included in the mesa stripe 610 which is a light emitting region and there are few crystal defects causing deterioration of the laser element. It is assumed that the active layer 605 contributes to light emission.

【0040】ところで、実施形態の1においてはレーザ
素子の劈開位置は選択成長マスク150の直上領域15
2外の部分に限られていた。これは、選択成長マスク1
50の直上領域152で劈開した場合に、レーザの発光
領域となるメサストライプ110内の破壊し易い劈開面
近傍に結晶欠陥が多く含まれる選択成長マスクの直上領
域152が包含され、素子を動作させた時に瞬時に劣化
することを避けるためである。しかし、実施形態1にお
けるように選択成長マスク150の直上領域152の近
傍にて選択成長マスク150の直上領域152に平行に
劈開をした場合、部分的に劈開面に段差が生じ、結果と
して一部の素子にてメサストライプ110に選択成長マ
スク150の直上領域152が含まれてしまう場合があ
った。これは、選択成長マスク150の直上領域152
に結晶欠陥が多く含まれており、結晶として弱く、より
割れやすいことが原因と考えられる。すなわち、選択成
長マスク150の直上領域152で結晶が劈開しやい性
質を持ち合わせているのに関わらず、実施形態1ではそ
の近傍を劈開していたためである。この現象は、劈開に
より素子を分割する場合のみならず、スクライブにより
素子を分割する場合にも同様の現象が観測され、選択マ
スク151の直上領域153でスクライブすした場合に
比べて、選択マスク151の直上領域153近傍で選択
マスク151の直上領域153と平行に制御性良くスク
ライブした場合の歩留まりは低かった。
Incidentally, in the first embodiment, the cleavage position of the laser element is set in the region 15 directly above the selective growth mask 150.
It was limited to two outside parts. This is the selective growth mask 1
When cleaved at the region 152 directly above the region 50, the region 152 directly above the selective growth mask, which contains many crystal defects near the easily broken cleavage plane in the mesa stripe 110, which becomes the laser emission region, is included, and the device is operated. This is to avoid instantaneous deterioration when the battery is damaged. However, when cleaving is performed in the vicinity of the region 152 directly above the selective growth mask 150 in parallel with the region 152 directly above the selective growth mask 150 as in the first embodiment, a step is partially generated in the cleavage plane, and as a result, a step is generated. In some devices, the region 152 directly above the selective growth mask 150 may be included in the mesa stripe 110. This is because the region 152 directly above the selective growth mask 150
Contains many crystal defects, and is considered to be a cause of being weak as a crystal and more easily broken. That is, regardless of the fact that the crystal has the property of being easily cleaved in the region 152 directly above the selective growth mask 150, the vicinity is cleaved in the first embodiment. This phenomenon is observed not only when the element is divided by cleavage but also when the element is divided by scribing. The same phenomenon is observed in the case where the selection mask 151 is scribed in the region 153 immediately above the selection mask 151. In the case where the scribe was performed with good controllability in the vicinity of the region 153 directly above and in parallel with the region 153 directly above the selection mask 151, the yield was low.

【0041】一方、本実施形態素子では、素子を分割す
る際の4面全てのスクライブによる素子分割位置を選択
成長マスク650、651の直上領域652、653に
限定できるため、素子分割時に所定の位置にてスクライ
ブが起こり、メサストライプ610に選択マスクの直上
領域652が含まれたり、所定の形状(上方から観察し
て図6に示すように直方形)から素子の形状がずれるこ
とは無かった。これにより、素子をマウントする際の素
子形状認識においても、エラーを低下させることがで
き、素子マウント歩留まりも改善することができた。こ
の点も、本実施形態素子における大きなメリットであっ
た。
On the other hand, in the device of the present embodiment, the device dividing position by scribing all four surfaces when dividing the device can be limited to the regions 652 and 653 immediately above the selective growth masks 650 and 651. No scribing occurred, and the mesa stripe 610 did not include the region 652 immediately above the selection mask, and the element shape did not deviate from a predetermined shape (a rectangular shape as viewed from above as shown in FIG. 6). As a result, errors can be reduced even in recognition of the element shape when mounting the element, and the element mounting yield can be improved. This point is also a great advantage of the device of the present embodiment.

【0042】(実施形態4)次に、成長抑制構造の直上
領域の活性層が素子に残存している場合の本発明の実施
形態を発光ダイオードの例を用いて説明する。図7に、
本実施形態の発光素子の上面より観察した構造図を示
す。GaN連続膜層の形成方法や半導体積層構造は実施
形態2の場合と同じとした(本実施形態例の説明では共
通する各層の標記は実施例2と同一とする)。実施形態
2と異なるのは、In0.45Ga0.55N単一量子井戸活性
層404を含むメサ710の形状が図7のような形状を
有しており、かつそのサイズを390μm角と大きくし
た点である。このため、本実施形態の発光素子では、n
−GaN連続膜層401成長時の成長抑制構造たる溝構
造450の直上領域751に位置するIn0.45Ga0.55
N単一量子井戸活性層404がメサ710内に含まれた
形となっている。
(Embodiment 4) Next, an embodiment of the present invention in which the active layer in the region immediately above the growth suppressing structure remains in the device will be described using an example of a light emitting diode. In FIG.
FIG. 2 shows a structural view of the light emitting device of the present embodiment as viewed from above. The method of forming the GaN continuous film layer and the semiconductor multilayer structure are the same as those of the second embodiment (the description of the present embodiment assumes that the common layers are the same as those of the second embodiment). The difference from the second embodiment is that the shape of the mesa 710 including the In 0.45 Ga 0.55 N single quantum well active layer 404 has a shape as shown in FIG. 7 and the size is increased to 390 μm square. is there. Therefore, in the light emitting device of the present embodiment, n
-In 0.45 Ga 0.55 located in the region 751 directly above the groove structure 450 as the growth suppressing structure during the growth of the -GaN continuous film layer 401
The N single quantum well active layer 404 is included in the mesa 710.

【0043】しかし、本実施形態の発光素子では、p型
電極711を300μm角として、メサ710の中央領
域に配置した。すなわち、溝構造450の直上領域75
1および直上領域751の端から30μmの領域におい
てはp型電極が形成されないようにした。一方、n型電
極712はIn0.45Ga0.55N単一量子井戸活性層40
4が除去された発光素子の一角に図7のように形成し
た。
However, in the light emitting device of the present embodiment, the p-type electrode 711 is 300 μm square and arranged in the center region of the mesa 710. That is, the region 75 immediately above the groove structure 450
No p-type electrode was formed in the region 30 μm from the end of the region 1 and the region 751 directly above. On the other hand, the n-type electrode 712 is composed of the In 0.45 Ga 0.55 N single quantum well active layer 40.
4 was formed at one corner of the light emitting element from which the light emitting element 4 was removed, as shown in FIG.

【0044】このような構成とすることにより、p型コ
ンタクト層406、p型電極711から注入される電流
はp−GaNコンタクト層406が、比較的抵抗率の高
いp−GaNからなっており、かつ0.4μmとその膜
厚が薄いために、p型コンタクト層406中ではほとん
ど電流が横方向に拡散せず、p型電極711の直下のI
0.45Ga0.55N単一量子井戸活性層404にのみ電流
を注入することができる。
With such a configuration, the current injected from the p-type contact layer 406 and the p-type electrode 711 is such that the p-GaN contact layer 406 is made of p-GaN having a relatively high resistivity. In addition, since the thickness is as small as 0.4 μm, almost no current is diffused in the p-type contact layer 406 in the lateral direction, and I
Current can be injected only into the n 0.45 Ga 0.55 N single quantum well active layer 404.

【0045】当該実施形態の発光素子の特性を評価した
結果、5%以上の電子−光子変換効率を有するチップ
は、検査した内の79%に達し、従来技術により構成さ
れた発光素子より格段の改善が認められた。また、これ
らの発光素子の信頼性試験(条件は実施形態2と同様)
を行ったところ、1000時間経過後の発光輝度は試験
当初の発光輝度に対して85〜99%の範囲となり、全
ての発光素子が実用上問題ないことが確認された。
As a result of evaluating the characteristics of the light emitting device of this embodiment, the number of chips having an electron-photon conversion efficiency of 5% or more reached 79% of the inspected devices, which is much higher than the light emitting device constructed by the conventional technology. Improvement was noted. In addition, reliability tests of these light emitting elements (the conditions are the same as in the second embodiment)
Was performed, the emission luminance after 1000 hours was in the range of 85 to 99% of the emission luminance at the beginning of the test, and it was confirmed that all the light emitting elements had no practical problem.

【0046】以上、実施形態の発光素子においては、G
aN連続膜半導体層を用いて窒化ガリウム系の発光素子
を作製した例を説明したが、本発明は以下のような場合
にも適用できることはいうまでもない。 (1)基板材料や連続膜半導体層の材料、および発光素
子を構成する材料が異なる場合(例えば、基板がSi、
連続膜半導体層がGaAs、の場合や基板がSi、Ga
Asで連続膜層がGaNである場合、等)。 (2)成長抑制構造である選択成長マスクの材料が異な
る場合(SiNx、SiOx、AlOx、等)や、構造自
体が選択成長マスクや溝構造以外の場合(例えば、サフ
ァイア基板上に形成したリッジストライプやその他の凹
凸構造、等)。 (3)連続膜半導体層を形成後、発光層形成前に基板を
完全に除去するように工程の順番を変更した場合。
As described above, in the light emitting device of the embodiment, G
Although an example in which a gallium nitride-based light emitting element is manufactured using an aN continuous film semiconductor layer has been described, it goes without saying that the present invention can be applied to the following cases. (1) When the material of the substrate, the material of the continuous film semiconductor layer, and the material constituting the light emitting element are different (for example, the substrate is Si,
When the continuous film semiconductor layer is GaAs, or when the substrate is Si, Ga
As, when the continuous film layer is GaN, etc.). (2) When the material of the selective growth mask which is the growth suppressing structure is different (SiN x , SiO x , AlO x , etc.) or when the structure itself is other than the selective growth mask or the groove structure (for example, formed on a sapphire substrate) Ridge stripes and other irregular structures, etc.). (3) When the order of the steps is changed so that the substrate is completely removed after the formation of the continuous film semiconductor layer and before the formation of the light emitting layer.

【0047】[0047]

【発明の効果】以上のように、本発明を適用することに
より、基板とは格子定数や熱膨張係数が異なる連続膜半
導体層上に半導体発光素子を作製した場合、発光効率の
低下を防止し、歩留まり良く発光効率の高い発光ダイオ
ードや半導体レーザを実現できた。また、本発明によ
り、これらの発光素子において実用上十分な信頼性を確
保することが可能となった。
As described above, by applying the present invention, when a semiconductor light emitting device is manufactured on a continuous film semiconductor layer having a lattice constant and a thermal expansion coefficient different from those of a substrate, a decrease in luminous efficiency is prevented. As a result, a light emitting diode or a semiconductor laser having a high luminous efficiency with a high yield can be realized. Further, according to the present invention, it is possible to secure practically sufficient reliability in these light emitting elements.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態1の半導体レーザ素子の断
面図である。
FIG. 1 is a sectional view of a semiconductor laser device according to a first embodiment of the present invention.

【図2】本発明の実施の形態1の半導体レーザ素子の作
製工程図である。
FIG. 2 is a manufacturing process diagram of the semiconductor laser device according to the first embodiment of the present invention;

【図3】成長マスクの直上領域からメサストライプまで
の距離に対するメディアン寿命を示す図である。
FIG. 3 is a diagram showing a median life with respect to a distance from a region immediately above a growth mask to a mesa stripe.

【図4】本発明の実施の形態2の半導体発光素子の断面
図である。
FIG. 4 is a sectional view of a semiconductor light emitting device according to a second embodiment of the present invention.

【図5】本発明の実施の形態2の半導体発光素子の作製
工程図である。
FIG. 5 is a manufacturing process diagram of the semiconductor light emitting device according to the second embodiment of the present invention.

【図6】本発明の実施の形態3の半導体レーザ素子の断
面図である。
FIG. 6 is a sectional view of a semiconductor laser device according to a third embodiment of the present invention.

【図7】本発明の実施の形態4の半導体発光素子の上面
図である。
FIG. 7 is a top view of a semiconductor light emitting device according to a fourth embodiment of the present invention.

【図8】従来の半導体発光素子の作製工程図である。FIG. 8 is a manufacturing process diagram of a conventional semiconductor light emitting device.

【図9】従来の半導体発光素子の構造を示す図である。FIG. 9 is a view showing a structure of a conventional semiconductor light emitting device.

【図10】成長抑制構造からの距離に対する結晶転移の
面密度を示す図である。
FIG. 10 is a diagram showing a surface density of crystal transition with respect to a distance from a growth suppressing structure.

【符号の説明】[Explanation of symbols]

100 サファイア基板 101、601 GaNバッファ層 102、602、401 n−GaN連続膜層 103、603、402 n−GaNバッファ層 104、604 n−Al0.1Ga0.9Nクラッド層 105、605 多重量子井戸活性層 106、606、405 p−Al0.1Ga0.9Nクラッ
ド層 107、607 406 p−GaNコンタクト層 110、610 メサストライプ 111、611、408、711 p型電極 112、612、407、712 n型電極 150、151、650、651 選択成長マスク 152、153、652、653 直上領域 400 サファイア基板 403 In0.2Ga0.8N歪み緩和層 404 In0.45Ga0.55N単一量子井戸活性層 410 メサ 450 溝構造 451、751 直上領域 600 SiC基板 710 メサ
Reference Signs List 100 sapphire substrate 101, 601 GaN buffer layer 102, 602, 401 n-GaN continuous film layer 103, 603, 402 n-GaN buffer layer 104, 604 n-Al 0.1 Ga 0.9 N cladding layer 105, 605 Multiple quantum well active layer 106, 606, 405 p-Al 0.1 Ga 0.9 N cladding layer 107, 607 406 p-GaN contact layer 110, 610 mesa stripe 111, 611, 408, 711 p-type electrode 112, 612, 407, 712 n-type electrode 150, 151, 650, 651 Selective growth mask 152, 153, 652, 653 Immediately above region 400 Sapphire substrate 403 In 0.2 Ga 0.8 N strain relaxation layer 404 In 0.45 Ga 0.55 N single quantum well active layer 410 Mesa 450 Groove structure 451, 751 Area 600 SiC Substrate 710 mesa

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 成長抑制構造上への結晶成長により得ら
れる成長抑制構造直上領域を含む連続膜半導体層と、光
を発生させる活性層とを有する半導体発光素子であっ
て、 該活性層の内、電流注入により光を発生する発光領域が
前記成長抑制構造直上領域以外の領域に形成されている
ことを特徴とする半導体発光素子。
1. A semiconductor light emitting device comprising: a continuous film semiconductor layer including a region immediately above a growth suppression structure obtained by growing a crystal on a growth suppression structure; and an active layer for generating light. A semiconductor light-emitting element, wherein a light-emitting region for generating light by current injection is formed in a region other than a region immediately above the growth suppressing structure.
【請求項2】 前記発光領域は成長抑制構造直上領域か
ら30μm以上離れた位置に形成されていることを特徴
とする請求項1に記載の半導体発光素子。
2. The semiconductor light emitting device according to claim 1, wherein the light emitting region is formed at a position separated from the region immediately above the growth suppressing structure by 30 μm or more.
【請求項3】 前記発光領域と前記成長抑制構造直上領
域との間の領域では、前記活性層が除去されていること
を特徴とする半導体発光素子。
3. The semiconductor light emitting device according to claim 1, wherein said active layer is removed in a region between said light emitting region and a region immediately above said growth suppressing structure.
【請求項4】 基板上に成長抑制構造を形成する第1工
程と、 前記基板および前記成長抑制構造の両方を連続して覆う
ように前記基板と格子定数または熱膨張係数が異なる連
続膜半導体層を形成する第2工程と、 前記連続膜半導体層の上に光を発生させる活性層を含む
多層構造体を形成する第3工程と、 前記成長抑制構造部の直上領域を除いて前記活性層にお
ける発光領域を規定するための構造を形成する第4工程
と、を有することを特徴とする半導体発光素子の製造方
法。
4. A first step of forming a growth suppressing structure on a substrate, and a continuous film semiconductor layer having a different lattice constant or thermal expansion coefficient from the substrate so as to continuously cover both the substrate and the growth suppressing structure. A second step of forming a multilayer structure including an active layer that generates light on the continuous film semiconductor layer; and a third step of forming a multilayer structure including an active layer that generates light on the continuous film semiconductor layer. A fourth step of forming a structure for defining a light emitting region.
【請求項5】 半導体発光素子をウェハーから複数個の
半導体発光素子に分割する工程を有する半導体発光素子
の製造方法であって、 前記第4工程後、前記成長抑制構造直上の前記活性層が
半導体発光素子に含まれないように半導体発光素子をウ
ェハーから分割する第5工程とを含むことを特徴とする
請求項4に記載の半導体発光素子の製造方法。
5. A method for manufacturing a semiconductor light emitting device, comprising: dividing a semiconductor light emitting device from a wafer into a plurality of semiconductor light emitting devices, wherein after the fourth step, the active layer immediately above the growth suppressing structure is a semiconductor. 5. The method according to claim 4, further comprising: dividing the semiconductor light emitting device from the wafer so as not to be included in the light emitting device.
【請求項6】 前記第5工程において、前記成長抑制構
造直上の端から30μm以内の領域に残存する前記活性
層が、半導体発光素子に含まれないように半導体発光素
子を分割することを特徴とする請求項5に記載の半導体
発光素子の製造方法。
6. The semiconductor light emitting device according to claim 5, wherein in the fifth step, the semiconductor light emitting device is divided such that the active layer remaining in a region within 30 μm from an end immediately above the growth suppressing structure is not included in the semiconductor light emitting device. A method for manufacturing a semiconductor light emitting device according to claim 5.
JP03563898A 1998-02-18 1998-02-18 Light emitting diode Expired - Fee Related JP4169821B2 (en)

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