JPH11274475A - Method for manufacturing heterojunction field-effect transistor and method for manufacturing semiconductor device - Google Patents

Abstract

(57) Abstract: In a heterojunction field-effect transistor, a resistance associated with a heterojunction is suppressed. A GaAs substrate is provided on a semi-insulating GaAs substrate.
s buffer layer 102, AlGaAs electron supply layer 103,
i-type In _0.2 Ga _0.8 As channel layer 104, n ⁺ type A
An lGaAs electron supply layer 105, an In _0.49 Ga _0.51 As contact layer 106, and an n ⁺ -type GaAs contact layer 107 having a planar doping layer 108 are sequentially stacked. A first opening 111 and a second opening 112 are formed. A gate electrode 113 is formed. Then 700
A heat treatment at 5 ° C. for 5 minutes is performed to repair damage introduced during the sputter deposition of WSiN, to diffuse Si from the Si planar doping layer 108, and to form an activated n-type diffusion region 111.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a heterojunction field-effect transistor having two types of semiconductor layers stacked and having a heterojunction, and a method of manufacturing a semiconductor device.

[0002]

2. Description of the Related Art A field effect transistor including a heterojunction has been increasing in importance year by year as a device constituting a microwave, millimeter wave, or ultra-high-speed digital circuit. Various structures and manufacturing methods of field effect transistors have been developed for the purpose of realizing high performance transistors and for the purpose of mass production and low cost production.

FIG. 5 is a sectional view showing the structure of a field effect transistor utilizing a two-dimensional electron gas accumulated at a hetero interface. Reference numeral 401 denotes a semi-insulating GaAs substrate; 402, a buffer layer made of GaAs or AIGaAs having high resistance; 403, a channel layer made of GaAs or InGaAs having a sufficiently low impurity concentration; Or In
An electron supply layer made of GaP, 405 is an n-type GaAs contact layer doped at a high concentration, 109 is a source electrode, 110 is a drain electrode, and 113 is a gate electrode.

[0004] The two-stage opening is provided in the contact layer 405 in order to increase the drain breakdown voltage and the gate breakdown voltage to enable a high output operation of the field effect transistor. However, when such a two-stage structure is formed by etching, it is not easy to control the etching depth uniformly in the wafer surface and with sufficient reproducibility for each wafer.

In order to solve this problem, a two-stage structure has been formed by employing a multilayer semiconductor layer made of a different material as a contact layer and imparting selectivity to etching. For example, as shown in FIG. 6, an InGaP contact layer 506 and a Ga
When the structure in which the As contact layer 507 is laminated is used, sufficient wet etching selectivity can be obtained between the GaAs contact layer 507 and the InGaP contact layer 506, and a uniform recess shape can be obtained with good reproducibility and in-plane. It is described in JP-A-7-335867 that it can be formed. In FIG. 5, reference numeral 501 denotes an AlGaAs electron supply layer.

The purpose of making the recess shape multi-stage is to improve the breakdown voltage of the hetero-junction field effect transistor and operate it with a large current as described above. For that purpose, it is preferable to use a compound semiconductor layer having as small an electron affinity as possible for the electron supply layer 404 in contact with the gate electrode 113 formed of a Schottky junction. 507 is added to the contact layer where the source / drain electrodes 109 and 110 are in contact.
In order to reduce the source resistance and the drain resistance, it is better to use a compound semiconductor layer having as large an electron affinity as possible.

[0007] To improve the breakdown voltage, all the materials from the source to the gate are involved. Therefore, it is preferable to select a material having a high withstand voltage against impact ionization at a high electric field, which is a main factor of withstand voltage breakdown.
It is preferable to use a semiconductor material having a small electron affinity.

However, when a material having a low electron affinity is used for the contact layer 506 and a material having a high electron affinity is used for the contact layer 507, a high hetero barrier is interposed between the contact layers 506 and 507. Therefore, the hetero-barrier acts as a resistor, increasing the source resistance, and hindering the performance enhancement of the transistor.

[0009]

As described above, in a heterojunction field effect transistor, in order to improve the breakdown voltage, a contact layer in contact with an electron supply layer and having a small electron affinity and a contact layer in contact with an ohmic electrode and having a large electron affinity are used. There is a problem that a high hetero barrier is formed between the contact layer and the contact layer, and the source / drain resistance is increased.

[0010] This problem is not a problem peculiar to the heterojunction field-effect transistor, but relates to a structure in which a second semiconductor layer having a higher electron affinity than the first semiconductor layer is stacked on the first semiconductor layer. Is also a problem that arises.

[0011] An object of the present invention is to provide a semiconductor device in which a second contact layer having a higher electron affinity than the first semiconductor layer is laminated on the first contact layer. It is an object of the present invention to provide a method for manufacturing a heterojunction field effect transistor and a method for manufacturing a semiconductor device, which can reduce the resistance between them.

[0012]

Means for Solving the Problems The gist of the present invention is to reduce the resistance associated with a hetero barrier between a semiconductor having a low electron affinity and a semiconductor having a high electron affinity by utilizing the diffusion of dopant atoms. To make it happen.

The present invention is configured as follows to achieve the above object. (1) The present invention (claim 1) provides a heterojunction field effect comprising a channel layer and an electron supply layer formed on the channel layer and having a smaller electron affinity and a wider band gap than the channel layer. Forming a first contact layer on the electron supply layer, wherein the first contact layer has a higher electron affinity than the first contact layer, is internally doped with an impurity, and Forming a second contact layer having a region in which the concentration of the impurity is higher than that of the surroundings, selectively forming a source electrode and a drain electrode on the second contact layer; A step of selectively etching the contact layer and a step of applying heat treatment to diffuse the impurity at least at an interface between the first contact layer and the second contact layer. And characterized in that: (2) The present invention (claim 2) provides a method for manufacturing a semiconductor device, comprising the steps of:
Forming a second semiconductor layer having a region having a higher electron affinity than the first semiconductor layer, having an impurity doped therein, and having a higher concentration of the impurity therein than the surroundings; Diffusing the impurity at the interface between the first semiconductor layer and the second semiconductor layer. (3) The present invention (claim 3) provides a method for manufacturing a semiconductor device, comprising the steps of:
Forming a second semiconductor layer having a region having a higher electron affinity than the first semiconductor layer, being doped with an impurity therein, and having an impurity concentration higher than the surroundings therein; Etching a predetermined region to expose the first semiconductor layer;
Diffusing the impurity at the interface between the first semiconductor layer and the second semiconductor layer.

Preferred embodiments of the present invention will be described below.
A second semiconductor of the first conductivity type having a higher electron affinity than the first semiconductor layer on the first semiconductor layer, a region doped with impurities therein, and a region in which the concentration of the impurities is higher than the surrounding region. Forming a layer, etching a predetermined region of the second semiconductor layer to expose the first semiconductor layer, and applying heat treatment to at least an interface between the first semiconductor layer and the second semiconductor layer. While diffusing the impurities,
Diffusing constituent elements of the first semiconductor layer and the second semiconductor layer mutually.

Forming a first contact layer of the first conductivity type on the electron supply layer of the hetero field effect transistor; and forming an electron affinity on the first contact layer higher than that of the first contact layer. Forming a second contact layer doped with an impurity of the first conductivity type and having a region in which the concentration of the impurity is higher than the surroundings;
Forming a source / drain electrode on the semiconductor layer, and exposing the first semiconductor layer by etching the second semiconductor layer using the source / drain electrode as a mask;
Performing a step of etching a predetermined region of the exposed first semiconductor layer to expose the electron supply layer, a step of forming a gate electrode on the exposed electron supply layer, and a heat treatment;
Diffusing the impurity layer at least at the interface between the first contact layer and the second contact layer.

A step of forming a first contact layer of the first conductivity type on the electron supply layer of the hetero field effect transistor; and a step of forming an electron affinity on the first contact layer higher than that of the first contact layer. Forming a second contact layer doped with an impurity of the second conductivity type and having a region in which the concentration of the impurity is higher than the surroundings;
Forming a source / drain electrode on the first contact layer, etching the second contact layer using the source / drain electrode as a mask to expose the first contact layer, and exposing the first contact layer A step of forming a gate electrode thereon and a heat treatment to keep the exposed first semiconductor layer of the second conductivity type and to set the first contact layer in the lower region of the second contact layer to the first conductivity type And a step of performing.

The first semiconductor layer is made of AlGaAs, InGa
P, InAlGaP, InP or InAlAs, and the second semiconductor layer is made of GaAs, AIGaAs, InG
aP, InP or InGaAs.

[Operation] The present invention has the following operation and effects by the above configuration. In a stacked structure of a first semiconductor layer having a small electron affinity and a second semiconductor layer having a large electron affinity in contact with this layer, when heat treatment is performed in a structure in which high concentration doping is performed in the second semiconductor layer, , The impurity diffuses from the second semiconductor layer toward the first semiconductor layer,
Is also heavily doped. As a result,
This heterojunction interface is doped at a high concentration, and the depletion width becomes narrow. Therefore, the tunnel current at the hetero barrier increases, and the resistance can be reduced.

If the conductivity of the second semiconductor layer is different from the conductivity type of the first semiconductor layer, the surface of the first semiconductor layer of the first conductivity type that is in contact with the second semiconductor layer is changed to the second conductivity type. In order to achieve this, it is necessary to dope the first semiconductor layer with an impurity at a high concentration.

When the impurity concentration becomes high, diffusion may be promoted more than the case where it is predicted by a diffusion coefficient considering concentration dependency. Therefore, by having a highly doped region in a part of the second semiconductor layer of the second conductivity type, the first semiconductor layer can be doped with a high concentration of impurity by diffusion in the heat treatment step. The surface of the first semiconductor layer can be changed to the second conductivity type in a short time.

Further, when heat treatment is performed after removing a predetermined region of the second semiconductor layer and exposing the first semiconductor layer,
No impurities are diffused into the exposed first semiconductor layer. According to the present invention, in order to form a multi-step recess shape, the contact layer is made of, for example, InGaP (first semiconductor layer) and GaAs.
When the present invention is applied to a heterojunction field-effect transistor in which the (second semiconductor layer) is stacked, impurities can be diffused below the region where the source / drain electrodes are formed, and the resistance can be reduced. Further, since no impurity is diffused on the exposed InGaP, the withstand voltage between the gate electrode and the InGaP increases. Therefore, in the present invention, the resistance accompanying the hetero barrier can be reduced by utilizing the diffusion of the dopant atoms after the formation of the recessed shape while utilizing the characteristics of the selective etching.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 is a process sectional view showing a manufacturing process of a heterojunction field effect transistor according to a first embodiment of the present invention.

First, as shown in FIG. 1A, a 500 nm-thick non-doped GaAs buffer layer 102 and an AlGaAs electron supply layer 1 are formed on a semi-insulating GaAs substrate 101.
03, an i-type In _0.2 Ga _0.8 As channel layer 104 having a thickness of 1.5 nm, an n ⁺ -type AlGaAs electron supply layer 105,
In _0.49 Ga _0.51 As contact layer 106 having a thickness of 30 nm doped with about 1 × 10 ¹⁷ cm ^{−3 of} Si;
A 50 nm-thick n ⁺ -type GaAs contact layer 107 doped with about 5 × 10 ¹⁸ cm ⁻³ is sequentially laminated.

During the growth of the GaAs contact layer 107, a 1 × 10 ¹³ cm ⁻² Si planar doping 108 is formed at a position 1 nm from the interface with the In _0.49 Ga _0.51 P contact layer 106.

The electron supply layer 1 of Al _0.2 Ga _0.8 As
03 is a 50 nm-thick non-doped AlGaAs, Si
Doped with about 3 × 10 ¹⁸ cm ⁻³ and having a film thickness of 5 nm
l _0.2 Ga _0.8 As, non-doped Al with a thickness of 1.5 nm
It is composed of _0.2 Ga _0.8 As. AlGa
The As electron supply layer 105 is made of non-doped Al having a thickness of 2 nm.
_0.2 Ga _0.8 As, Si is doped with about 2 × 10 ¹⁸ cm ^{−3, and} 15 nm thick Al _0.2 Ga _0.8 As, Si is 1 ×
Al _0.2 G with a thickness of 15 nm doped about 10 ¹⁷ cm ^-3
a _0.8 As.

This structure is grown by a metal organic chemical vapor deposition method, and the growth material is trimethylgallium (CH).
₃ ) ₃ Ga, trimethylaluminum (CH ₃ ) ₃ A
1, trimethylindium (CH ₃ ) ₃ In, arsine AsH ₃ , and disilane Si ₂ H ₆ as a dopant material.

Next, after performing element isolation by wet etching, as shown in FIG. 1B, a source electrode 109 and a drain electrode 1 are formed on the GaAs contact layer 107.
Form 10. And H ₃ PO ₄ —H ₂ O ₂ —H ₂
The GaAs contact layer 10 is formed using an O-based etchant.
7 is selectively etched to form a first opening 111. Since the H ₃ PO ₄ —H ₂ O ₂ —H ₂ O-based etchant hardly etches InGaP, the etching stops at the surface of the InGaP contact layer 106.

Then, using the diluted HCl, InGa
The P contact layer 106 is selectively etched to form a second opening 112. Since HCl can hardly etch AlGaAs, AlGaAs
Etching stops on the surface of the electron supply layer 105.

Then, after forming a resist pattern (not shown) having an opening in a region where the gate electrode is to be formed, WSiN is sputter deposited and the resist pattern is removed to form a gate electrode 113.

Thereafter, as shown in FIG. 1C, a protective film (not shown) made of a silicon nitride film is deposited by a plasma CVD method. Next, a heat treatment is performed at 700 ° C. for 5 minutes to repair damage introduced during sputtering deposition of WSiN, to diffuse Si from the Si planar doping layer 108, and to activate the n-type diffusion region 11.
4 is formed.

When the profiles of Si before and after the heat treatment were compared, it was confirmed that Si was diffused. If there is no diffusion region 114, InGaP and GaAs
Although the resistance based on the hetero barrier with s is large, the resistance can be reduced and the source resistance and the drain resistance can be reduced by forming the diffusion region.

In the InGaP contact layer 106, the portion where the n ⁺ -type GaAs contact layer is etched and the surface is exposed has no Si diffusion and the doping concentration is kept low, so that a high breakdown voltage is secured. can do. It is preferable that the Si doping amount is higher, but it is sufficient if the Si doping amount is at least 6 × 10 ¹² cm ⁻² .

In the transistor, the doped region is not limited to the GaAs contact layer 107. When diffusing impurities from a high-concentration doping layer, performance may deteriorate if diffusion occurs in other doping layers.

In general, the diffusion coefficient D (T) of an impurity atom at a temperature T is represented by D (T) = D ₀ EXP (−E / kT) (1) E is activation energy and k is Boltzmann's constant. Note that D ₀ is generally regarded as a constant, but is called a frequency term or an entropy term because it includes the frequency and activation energy of lattice vibration.

The equation (1) is well applied when the dopant concentration is low. However, the diffusion coefficient has a concentration dependence, and when the concentration is high, diffusion multiplies. For example, it is known that when Be, Zn, or the like becomes a certain concentration or more, the ratio existing at the interstitial position increases, and the diffusion shows larger diffusion than the temperature dependence of the diffusion coefficient.

Accordingly, the Si planar doping layer 10 in which Si is present at a high concentration in the GaAs contact layer 107 is formed.
Diffusion is caused by multiplication by 8 and Si can be sufficiently diffused to the interface with the InGaP contact layer by heating for a short time. At the same time, diffusion in another doping layer can be suppressed.

In order to dope Si into the GaAs contact layer 107 at a high concentration, it is preferable to perform planar doping of Si as shown in this embodiment. When Si is planar-doped in GaAs, Si is activated up to about 5 × 10 ¹² cm ⁻² ,
If the concentration is higher than this, the activation rate of Si decreases and saturates. When there is excess Si, the diffusion becomes larger than predicted by the equation (1) as described above,
In other layers doped with Si, only diffusion from the planar doping layer can be promoted without significant diffusion.

[Second Embodiment] FIG. 2 is a process sectional view showing a manufacturing process of a heterojunction field effect transistor according to a second embodiment of the present invention. In FIG. 2, the same portions as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

First, a substrate having a plurality of compound semiconductor layers epitaxially grown thereon as shown in FIG.
iO ₂ film (not shown) is formed on the n ⁺ -type contact layer 107, as a mask the SiO ₂ film, an acceleration voltage 30ke
B ions are implanted with V to form an impurity ion implanted region 201 (FIG. 2A). The crystal structure is destroyed by the ion implantation of B ions, and lattice defects occur.

The Si planar doping layer 108 of the epitaxial substrate of this embodiment is different from that of the first embodiment in that the In _0.49 Ga
It is inserted at a position 1.5 nm from the interface of the _0.51 P contact layer 106.

Then, as in the first embodiment, after element isolation, the source electrode 109, the drain electrode 110,
A first opening 111, a second opening 112, and a gate electrode 113 are formed.

Thereafter, a protective film (not shown) made of SiN is formed on the entire surface by a plasma CVD method.
A heat treatment is performed at 5 ° C. for 5 minutes to remove the protective film. This heat treatment has two purposes. One is to repair damage introduced during sputter deposition of WSiN at the time of forming the gate electrode 112, as in the first embodiment.

The second is to repair the crystal structure destroyed by the implantation of B ions, and to diffuse and activate Si in the Si planar doping layer 108 to form an n-type diffusion region 114. The purpose is to promote mutual diffusion of atoms at the heterojunction interface between the InGaP contact layer 106 and the GaAs contact layer 107 and between the InGaP contact layer 106 and the AIGaAs electron supply layer 205.

Since lattice defects have occurred in the crystal due to implantation of B ions, diffusion of Si occurs more easily than in the first embodiment. In addition, due to the presence of lattice defects, the InGaP contact layer 1
An InGaAsP transition layer (not shown) having a small mixed crystal ratio is formed at the interface between the GaAs contact layer 106 and the GaAs contact layer 107. Therefore, the resistance can be reduced as compared with the first embodiment, and the source resistance and the drain resistance can be reduced.

This will be further described. Diffusion of atoms also depends largely on lattice defects and strain in the crystal. If the concentration of vacancies greatly exceeds the thermal equilibrium concentration due to ion implantation or particle beam irradiation, the diffusion coefficient is locally increased. .

If the lattice defect concentration is high, not only the dopant atoms but also the atoms constituting the semiconductor layer are diffused during the heat treatment for diffusing the dopant. In particular, in the case where diffusion of atoms occurs at the hetero interface, the steepness of the hetero interface is reduced and the mixed crystal ratio is equivalently inclined. In this case, the height of the hetero barrier is reduced as compared with an interface having a steep mixed crystal ratio. By utilizing the diffusion of the dopant atoms and the diffusion of the constituent elements of the base semiconductor, the resistance associated with the hetero barrier can be further reduced.

As shown in this embodiment, by diffusing the constituent elements of the semiconductor layer simultaneously with the diffusion of the dopant, the interface has a structure in which the mixed crystal ratio is equivalently inclined,
The effective height of the hetero barrier is reduced, and the resistance associated with the hetero barrier can be reduced.

[Third Embodiment] FIG. 3 is a sectional view showing the structure of a heterojunction field effect transistor according to a third embodiment of the present invention. In this embodiment, an epitaxial growth layer having the following structure is used.

The difference between the epitaxial substrate used in the present embodiment and the previous embodiment is that about 1 × 10 ¹⁷ cm ⁻³ of Si exists between the n ⁺ -type InGaP electron supply layer 105 and the InGaP contact layer 106. 30n doped film thickness
m Al _0.2 Ga _0.8 AsAlGaAs contact layer 3
01 is inserted, and the InGaP contact layer 106 and n ⁺
1 × 10 between the GaAs contact layer 107
Al _0.2 Ga doped to about ¹⁸ cm ^-3 and having a thickness of 15 nm
_0.8 As contact layer 302 and 1 × 10 ¹⁸ c of Si
This means that an InGaP wide contact layer 303 with a thickness of 10 nm doped with about m ⁻³ is inserted.

The process for forming the transistor is almost the same as in the first embodiment. After performing element isolation by wet etching, a source electrode 108 and a drain electrode 109 are formed.

A first-stage opening 311 is formed in the GaAs contact layer 107 using an H ₃ PO ₄ —H ₂ O ₂ —H ₂ O-based etchant. Then I was diluted with HCl
The nGaP wide contact layer 303 is etched, followed by _{H 3 PO 4 -H 2 O 2} -H 2 O -based etchant AlGaAs contact layer 302 using etching,
The second opening 31 having a smaller opening width than the first opening 311
Form 2

Next, a third opening 313 having a narrow opening width is formed in the InGaP contact layer 106, and an AlGaAs
The contact layer 301 is exposed. Next, a gate electrode 113 made of WSiN is formed by sputter deposition.

Thereafter, a protective film made of SiN (not shown)
Is deposited by a plasma CVD method. Next, at 700 ° C,
A heat treatment for 5 minutes is performed to repair the damage introduced during the sputtering deposition of WSiN and to form the n-type diffusion region 114.

As shown in the present embodiment, the resistance based on the hetero-barrier can be reduced by using the Si diffusion region even in the case of forming an etching shape having a multistage opening.

[Fourth Embodiment] FIG. 4 is a process sectional view showing a manufacturing process of a heterojunction field effect transistor according to a fourth embodiment of the present invention.

First, as shown in FIG. 4A, a 500 nm-thick non-doped GaAs buffer layer 102 and an AlGaAs electron supply layer 1 are formed on a semi-insulating GaAs substrate 101.
03, non-doped Al _0.2 Ga _0.8 A with a thickness of 1.5 nm
s AlGaAs electron supply layer 103, InGaP
Electron supply layer 105, 5 × 10 ¹⁶ cm ⁻³ doped In
P-type InGaP contact layer 6 made of _0.49 Ga _0.51 P
A GaAs contact layer 107 having a thickness of 50 nm and doped with about 0.6 × 10 ¹⁸ cm ^{−3 of} Si and Si is sequentially stacked.

When forming the GaAs contact layer 107, a 1 × 10 ¹³ cm ⁻³ Si planar doping layer 108 is inserted at a position 1 nm from the interface with the In _0.49 Ga _0.51 P contact layer 606.

Note that the AlGaAs electron supply layer 103 is
Non-doped AlGaAs with a thickness of 50 nm and Si
5 nm thick n-type Al _0.2 doped at about 10 ¹⁸ cm ^-2
It is composed of Ga _0.8 As10.

The InGaP electron supply layer has a thickness of 2n.
2 × 10 m non-doped In _0.49 Ga _0.51 P and Si
In _0.49 Ga with a thickness of 15 nm doped about ¹⁸ cm ⁻³
_0.51 P.

Next, as shown in FIG. 4B, after element isolation is performed by wet etching, a source electrode 109 is formed.
And a drain electrode 110 are formed. And H ₃ PO
N ⁺ -type G by using a _4- H ₂ O ₂ -H ₂ O-based etchant
An opening is formed in the aAs contact layer 107, and the p ^- type I
The nGaP contact layer 606 is exposed.

Then, as shown in FIG.
A gate electrode 113 made of N is formed by sputtering deposition. Then, after forming a protective film (not shown) made of SiN by a plasma CVD method, a heat treatment is performed at 700 ° C. for 5 minutes.

This heat treatment has two purposes, one of which is to repair damage introduced during sputter deposition of WSiN. The other is to diffuse the Si of the Si planar doped layer 108 to form an activated n-type diffusion region 614.

By the diffusion of Si, the conductivity type of the p ⁻ -type InGaP contact layer 606 under the source and drain electrodes 109 and 110 is inverted from p-type to n-type, and n-type InG
An aP contact layer 615 is formed.

Therefore, the n ⁺ -type GaAs contact layer 1
07 and the n-type InGaP contact layer 615, the same n-type layer is continuous at the heterojunction interface. In addition, since the junction interface is highly doped with n-type impurities,
GaP contact layer 615 and GaAs contact layer 10
7, the resistance based on the heterojunction with
Source resistance and drain resistance can be reduced.

On the other hand, InG exposed by etching
Si is not diffused into the aP contact layer 606, and the conductivity type is kept p-type. Therefore, the Schottky barrier can be maintained higher than that of the n-type, the gate leakage current is reduced,
High gate breakdown voltage can be secured. It is preferable that the Si doping ratio of the Si planar doping layer 108 is high, but it is sufficient that the Si doping ratio is 1 × 10 ¹² cm ⁻² or more.

The present invention is not limited to the above embodiment. For example, the present invention is not limited to a hetero field effect transistor, but is applied to a structure in which a second semiconductor layer having a higher electron affinity than the first semiconductor layer is formed on the first semiconductor layer. be able to.

Although Si is used as the n-type dopant, the present invention is not limited to Si. For an n-type dopant, Sn, Te, S, or the like can be used. Also, p
In the case of a mold, Zn, Be, Hg, and C can be used. However,
In the case of C, since the diffusion is small, the position where the planar doping is inserted is set at 1 position from the compound semiconductor layer having a small electron affinity.
A position of about 2 to about 2 atomic layers is desirable.

In the second embodiment, B is used as the impurity to be ion-implanted. However, the same effect can be obtained with H, Ar, O, etc. by selecting the acceleration voltage and the dose.

In the above embodiment, the field effect transistor has been described. However, the application of the present invention is not limited to the embodiment. For example, MES
FET, InP, InGaAs, In other than GaAs
Application to a heterojunction field effect transistor using AlAs, InP, or the like as a constituent material is also possible.

In a heterojunction bipolar transistor, for example, an n-InGaP emitter layer and a GaAs
A hetero barrier exists as in the combination of the s emitter contact layers. n-AIGaAs emitter layer and GaAs
In the case of the combination of the emitter contact layers, an AlGaAs layer having a mixed crystal ratio is inserted between the two layers to eliminate an effective barrier and reduce the resistance. However, I
Inserting, for example, an InGaAsP layer with an inclined mixed crystal ratio at the interface between nGaP and GaAs has a problem that controllability and reproducibility during epitaxial growth are likely to be poor. Even in such a case, by diffusing a high concentration of n-type dopant from the GaAs contact layer side, the tunnel current can be increased and the resistance based on the hetero barrier can be reduced. In addition, the present invention does not depart from the gist thereof,
Various modifications are possible.

[0071]

As described above, according to the present invention, a second semiconductor layer having a high-concentration impurity layer is formed on a first semiconductor layer, and a heat treatment is carried out, whereby a heterojunction barrier is formed. Resistance can be reduced.

[Brief description of the drawings]

FIG. 1 is a process cross-sectional view showing a manufacturing process of a heterojunction field effect transistor according to a first embodiment.

FIG. 2 is a process cross-sectional view showing a manufacturing process of a heterojunction field effect transistor according to a second embodiment.

FIG. 3 is a cross-sectional view illustrating a configuration of a heterojunction field effect transistor according to a third embodiment.

FIG. 4 is a process cross-sectional view showing a manufacturing process of a heterojunction field effect transistor according to a fourth embodiment.

FIG. 5 is a cross-sectional view illustrating a configuration of a conventional heterojunction field effect transistor.

FIG. 6 is a cross-sectional view showing a configuration of a conventional heterojunction field-effect transistor.

[Explanation of symbols]

101 ... semi-insulating GaAs substrate 102 ... undoped GaAs buffer layer 103 ... AlGaAs electron supply layer 104 ... i-type In _0.2 Ga _0.8 As channel layer 105 ... n ⁺ -type AlGaAs electron supply layer 106 ... In _0.49 Ga _0.51 As contact layer 107 ... n ⁺ -type GaAs contact layer 108: Si planar doping layer 109: source electrode 110, drain electrode 111, first opening 112, second opening 113, gate electrode 114, n-type diffusion layer 201, impurity ion implantation region 301 AlGaAs contact layer 302 AlGaAs contact layer 303 InGaP wide contact layer 311 first opening 312 second opening 313 third opening 606 p ^- type InGaP contact layer 614 n-type diffusion Region 615: n-type InG P contact layer

Claims (3)

[Claims] 1. A method of manufacturing a hetero-junction field-effect transistor comprising a channel layer and an electron supply layer formed on the channel layer and having a smaller electron affinity and a wider band gap than the channel layer, Forming a first contact layer on the electron supply layer; and, on the first contact layer, having a higher electron affinity than the first contact layer, being doped with impurities inside, and having a concentration of the impurities inside. Forming a second contact layer having a region higher than the surroundings; selectively forming a source electrode and a drain electrode on the second contact layer; Selectively etching the second contact layer, and applying heat treatment to at least an interface between the first contact layer and the second contact layer. Method of manufacturing a heterojunction field effect transistor which comprises a step of diffusing the impurity. 2. A second semiconductor having, over the first semiconductor layer, a region having a higher electron affinity than the first semiconductor layer, doped with an impurity therein, and having a higher concentration of the impurity than the surrounding region. A method for manufacturing a semiconductor device, comprising: a step of forming a layer; and a step of performing heat treatment to diffuse the impurity at least at an interface between the first semiconductor layer and the second semiconductor layer. 3. A second semiconductor having a higher electron affinity on the first semiconductor layer than the first semiconductor layer, an impurity doped therein, and a region in which the concentration of the impurity is higher than that of the surroundings. Forming a layer; etching a predetermined region of the second semiconductor layer to expose the first semiconductor layer; applying heat treatment to at least an interface between the first semiconductor layer and the second semiconductor layer. And a step of diffusing the impurity.