JPH11307937A - Core board, its manufacturing method, and multi-layer printed circuit board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a core board with fine-pitch connection between upper and lower sides, its manufacturing method, and a multi-layer printed circuit board. SOLUTION: A resist 12 with an opening 12a is formed (step B), and a plating step is carried out for the opening 12a to form a conductive pole 14 as a through hole (step C). The conductive pole 14 is hardened with resin 16 (step E). Since the opening 12a formed in the resist 12 can be made smaller than a hole drilled in a through-hole formation step, the fine-pitch connection between the upper and lower sides can be formed by using the conductive pole 14 formed in the opening 12a with a small diameter.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a core substrate for a multilayer printed wiring board in which interlayer resin insulating layers, via holes and conductive circuits are alternately laminated, a method of manufacturing the core substrate, and the core substrate. The present invention relates to a multilayer printed wiring board using the same.

[0002]

2. Description of the Related Art In a build-up type multilayer printed wiring board, interlayer resin insulating layers and conductor layers are alternately laminated on both surfaces of a core substrate. Here, as the core substrate, a resin substrate obtained by laminating a plurality of prepregs obtained by impregnating a glass fiber with a resin is used. Through holes for connection between the upper and lower layers provided on the core substrate are formed by drilling through holes in the resin substrate with a drill, and depositing a plating film in the through holes.

[0003]

However, in the core substrate of the prior art, a through hole having a diameter of 0.3 mm or less could not be formed. That is, in the drill, 0.3
Since it is difficult to form a through hole having a diameter of less than mm, this determines the diameter of the through hole, which is an obstacle to the fine pitch of the core substrate.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a core substrate capable of taking up and down connections at a fine pitch, a method of manufacturing a core substrate, and a multilayer substrate. It is to provide a printed wiring board.

[0005]

According to the first aspect of the present invention, a core substrate is provided.
In order to achieve the above object, a technical feature is that the conductor pillar is fixed with a resin.

The technical feature of the core substrate according to claim 2 is that the diameter of the conductive pillar is 0.25 mm or less and 0.05 mm or more.

A third aspect of the present invention is the core substrate according to the first or second aspect, wherein the resin is a thermoplastic resin.

[0008] The method of manufacturing a core substrate according to claim 4 is characterized in that:
Technical features include the following steps (a) to (d). (A) forming a resist having an opening on a conductor, (b) forming a conductive column by plating the opening, (c) removing the resist, and (d) between the conductive columns. The step of filling the resin.

Further, a method of manufacturing a core substrate according to claim 5 is
Technical features include the following steps (a) to (e). (A) forming a resist having an opening on a conductor, (b) forming a conductive column by plating the opening, (c) removing the resist, and (d) between the conductive columns. The step of filling the resin. (E) polishing the upper portion of the filled resin to expose the conductive columns.

[0010] The method for manufacturing a core substrate according to claim 6 is characterized in that:
According to a fourth aspect of the present invention, in the step of forming the conductive pillar by the plating, the conductive pillar is formed by electrolytic plating.

A seventh aspect of the present invention is a multilayer printed wiring board in which interlayer resin insulating layers, via holes, and conductive circuits are alternately laminated on a core substrate, wherein the core substrate has conductive pillars fixed with resin. A technical feature is that the via hole is formed immediately above the conductive pillar of the core substrate.

According to the first aspect of the present invention, the conductive pillar having a function as a through hole is fixed with resin, and it is not necessary to form a through hole by drilling a through hole. By using it, the upper and lower connections can be made at a fine pitch.

According to a second aspect of the present invention, the diameter of the conductive pillar of the core substrate is set to 0.1.
It is 25 mm or less. Here, when it exceeds 0.25 mm, a through hole can be formed by a drill. On the other hand, the diameter of the conductive pillar is 0.05 mm or more. This is because when a conductive pillar having a height corresponding to the thickness of the core substrate (for example, 0.3 mm) is formed in the opening of the resist, if the diameter of the opening is 0.05 mm or less, the plating solution flows around. This is because it is difficult to form conductive columns.

According to the third aspect of the present invention, the resin for fixing the conductor pillars is thermoplastic, and therefore has good electrical characteristics such as a dielectric constant, and can be used for a high-frequency multilayer printed wiring board. .

In the method of manufacturing a core substrate according to a fourth aspect of the present invention, a resist having an opening is formed, and the opening is plated to form conductive pillars functioning as through holes, and the conductive pillars are solidified with resin to form a core substrate. . Here, the opening provided in the resist can be formed to have a smaller diameter than a through hole formed by a drill used in forming a through hole. Therefore, by using a conductive column formed in the small-diameter opening, the upper and lower connections can be formed at a fine pitch. Can take.

According to a fifth aspect of the present invention, a resist having an opening is formed, a plating is performed on the opening to form a conductive column functioning as a through hole, and the conductive column is solidified with a resin to form a core substrate. . Here, the opening provided in the resist can be formed to have a smaller diameter than a through hole formed by a drill used in forming a through hole. Therefore, by using a conductive column formed in the small-diameter opening, the upper and lower connections can be formed at a fine pitch. Can take. Further, since the upper portion of the filled resin is polished to expose the conductive columns, the connection between the upper layer and the conductive columns can be reliably established.

In the method of manufacturing a core substrate according to the sixth aspect, since the conductive columns are formed by electrolytic plating, they can be formed inexpensively and quickly.

In the multilayer printed wiring board according to the present invention, the core substrate is formed by fixing the conductor pillars with resin, and it is not necessary to form a through hole by drilling a through hole. Can take a connection. here,
Even if the upper and lower connections are made at a fine pitch by the conductive pillars, the pads for connecting to the via holes are formed on the core substrate, and by providing the pads, the conductive pillars cannot be provided at a fine pitch. For this reason, in the configuration of claim 7, the via hole is formed directly above the conductive pillar of the core substrate,
Eliminates pads and allows up and down connections with fine pitch.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A multilayer printed wiring board according to an embodiment of the present invention and a core substrate used for the multilayer printed wiring board will be described below with reference to the drawings. FIG.
2 shows a cross section of a core substrate according to an embodiment. The core substrate 30 is formed by fixing cylindrical conductive pillars 14 with a resin 16. The conductive pillars 14 function as through holes in a prior art core substrate.

The core substrate 30 is formed with a thickness of 0.3 mm. The conductive pillar 14 has a diameter of 0.1 mm. Here, it is desirable that the conductive pillars 14 are not more than 0.25 mm and not less than 0.05 mm. This is 0.2
If it exceeds 5 mm, it is possible to form a through hole by drilling as in the prior art. On the other hand, the diameter of the conductive pillar is desirably 0.05 mm or more. This is because when a conductive pillar having a height corresponding to the thickness (0.3 mm) of the core substrate is formed in the opening of the resist as described later, if the opening diameter is 0.05 mm or less, the plating solution is This is because the wraparound is poor and it is difficult to form conductive columns.

It is desirable to use a thermoplastic resin such as a fluorine resin (for example, polytetrafluoroethylene) as a resin for fixing the conductor columns. This is because the thermoplastic resin has good electrical characteristics such as a dielectric constant and can be suitably used for a high-frequency multilayer printed wiring board.

FIG. 7 shows a cross section of a multilayer printed wiring board using the core substrate 30. Build-up wiring layers 90A and 90B are formed on the front and back surfaces of the multilayer core substrate 30. The built-up layers 90A and 90B include an interlayer resin insulation layer 50 having via holes 60 and conductor circuits 58 formed therein, and an interlayer resin insulation layer 150 having via holes 160 and conductor circuits 158 formed therein.

On the front side, solder bumps 76U for connection to bumps (not shown) of the IC chip are formed, and on the back side, solder bumps 76D for connection to bumps (not shown) of the motherboard are formed. Are formed. In a multilayer printed wiring board, solder bumps 7 connected to IC chips
A conductor circuit from 6U is connected to a solder bump 76D connected to the motherboard. The front side built-up layer 90A and the back side built-up layer 90B are
It is connected via a conductive pillar 14 formed at zero.

Here, via holes 60 are connected via conductive layers 24 directly above the conductive pillars 14 of the core substrate. The conductor circuit 58 provided in the interlayer resin insulation layer 50 is connected to a via hole 60 (not shown). The conductor circuit 58 includes an upper via hole 16.
0, and solder bumps 76U and 76D are formed on the via hole 160 or on the conductor circuit 158 connected to the via hole 160 (not shown in the figure).

In this multilayer printed wiring board, the via hole 60 is formed immediately above the conductive pillar 14 which functions as a via hole, thereby eliminating the via hole connection pad used in the prior art. That is, since no pads are provided on the surface of the core substrate 30, conductive columns are arranged at a fine pitch, and the upper and lower connections are established.

Subsequently, a method of manufacturing the core substrate shown in FIG. 2F will be specifically described with reference to FIG. First, as shown in FIG. 1A, a commercially available resist film 11 having a thickness of 0.3 mm is adhered onto the copper foil 10. next,
A photomask film (not shown) on which a 0.1 mmφ black circle is printed is brought into close contact with the photomask film, and 500 mJ using an ultra-high pressure mercury lamp.
/ Cm ² . This is spray-developed with a DMTG solution, and as shown in FIG. 1 (B), has a 0.1 mmφ opening (opening for forming a conductive pillar) 12a having excellent dimensional accuracy equivalent to a photomask film. A 3 mm resist 12 is formed. Continuously, copper foil 10 under the following conditions
Then, a current is applied to the opening 12a, and electrolytic copper plating is performed in the opening 12a to form a conductive pillar 14 having a height of 0.3 mm. In addition, resist 1
2 can be formed to have a smaller diameter than a through hole formed by a drill used in forming a through hole used in the prior art, so that the conductive column 1 is provided in the small diameter opening 12a.
By forming 4, the upper and lower connections can be made at a fine pitch. [Electroplating aqueous solution] Sulfuric acid 180 g / l Copper sulfate 80 g / l Additive (manufactured by Atotech Japan, trade name: Capparaside GL) 1 ml / l [Electroplating conditions] Current density 1 A / dm ² Temperature Room temperature

Next, the resist 12 is stripped with 5% KOH (FIG. 1D). Then, a fluororesin (polytetrafluoroethylene or the like) 16 which is a thermoplastic resin is heated to about 370 ° C. which is a plasticizing temperature, applied and filled in the conductive pillars 14, cooled, and cured. Here, the multilayer printed wiring board used as the core substrate is used at a temperature lower than the plasticization temperature of the fluororesin and lower than 300 ° C. In the present embodiment, a fluororesin is used as a resin for fixing the conductive columns 14, but various resins such as an epoxy resin, a polyimide resin, and a bismaleimide triazine resin can be used.
Further, these resins may contain particles such as resin particles.

Finally, as shown in FIG. 2F, the upper portion is polished with the resin 16 to expose the conductive pillars 14, thereby ensuring the connection with the upper layer (conductor layer 24). Similarly, the lower copper foil 10 is polished to expose the conductive pillars 14, thereby ensuring connection with the lower layer (conductor layer 24). In the present embodiment, the lower copper foil 10 is once peeled off by polishing, but the copper foil 10 may be etched to form a conductor layer 24 described later.

Next, a method for manufacturing a multilayer printed wiring board using the core substrate will be described. The method described below relates to a method of manufacturing a multilayer printed wiring board by a semi-additive method, but the method of manufacturing a multilayer printed wiring board in the present invention employs a full additive method, a multi-lamination method, and a pin lamination method. can do. First, a method of manufacturing a multilayer printed wiring board according to the present embodiment will be described. Adhesive for electroless plating, B. Interlayer resin insulation, C.I. The composition of the resin filler will be described.

A. Raw material composition for preparing adhesive for electroless plating (adhesive for upper layer) [Resin composition] 25% acrylate of cresol novolac type epoxy resin (Nippon Kayaku, molecular weight 2500) at 80 wt% concentration in DMDG 35 dissolved resin solution
Parts by weight, photosensitive monomer (Toa Gosei Co., Aronix M
315) 3.15 parts by weight of an antifoaming agent (manufactured by San Nopco, S-
65) 0.5 parts by weight and 3.6 parts by weight of NMP are obtained by stirring and mixing.

[Resin composition] 12 parts by weight of polyether sulfone (PES), 7.2 parts by weight of an epoxy resin particle (manufactured by Sanyo Chemical Industries, polymer pole) having an average particle size of 1.0 μm, 7.2 parts by weight, and an average particle size of 0.1 part After mixing 3.09 parts by weight of a 5 μm one, 30 parts by weight of NMP is further added, and the mixture is stirred and mixed by a bead mill.

[Curing Agent Composition] 2 parts by weight of an imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Chemicals), a photoinitiator (Irgacure I-907, manufactured by Ciba Geigy) 2
Parts by weight, photosensitizer (DETX-S, manufactured by Nippon Kayaku) 0.2
Parts by weight and 1.5 parts by weight of NMP are obtained by stirring and mixing.

B. Raw material composition for preparing interlayer resin insulation agent (adhesive for lower layer) [Resin composition] 25% acrylate of cresol novolac type epoxy resin (Nippon Kayaku, molecular weight 2500) is dissolved in DMDG at a concentration of 80 wt%. 35 liquid resin
Parts by weight, photosensitive monomer (Toa Gosei Co., Aronix M
315) 4 parts by weight, an antifoaming agent (manufactured by San Nopco, S-65)
0.5 parts by weight and 3.6 parts by weight of NMP are obtained by stirring and mixing.

[Resin Composition] 12 parts by weight of polyethersulfone (PES) and 1 particle of epoxy resin particles (manufactured by Sanyo Chemical Industries, polymer pole) having an average particle size of 0.5 μm were used.
After mixing 4.49 parts by weight, 30 parts by weight of NMP is further added, and the mixture is stirred and mixed by a bead mill.

[Curing Agent Composition] 2 parts by weight of an imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Chemicals), 2 parts by weight of a photoinitiator (Irgacure I-907, manufactured by Ciba Geigy), a photosensitizer (Nippon Kayaku) And 0.2 parts by weight of DETX-S) and 1.5 parts by weight of NMP.

C. Raw material composition for preparing resin filler [Resin composition] 100 parts by weight of bisphenol A type epoxy monomer (manufactured by Yuka Shell, Epicoat 828), 150 parts by weight of Al ₂ O ₃ spherical particles having an average particle size of 1.5 μm on the surface , 30 parts by weight of N-methylpyrrolidone (NMP) and 1.5 parts by weight of a leveling agent (manufactured by San Nopco, Perenol S4) were stirred and mixed, and the viscosity of the mixture was adjusted to 23 ± 1 ° C.
Adjust to 5,000-49,000 cps.

[Curing agent composition] 6.5 parts by weight of an imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Chemicals).

Next, the manufacturing process of the printed wiring board will be described with reference to FIGS. (1) First, a plated copper film 22 is formed by performing electroless plating and electrolytic plating on both surfaces of the core substrate 30 shown in FIG. 2 (F) (FIG. 2 (G)). Next, the conductor layer 24 for connection to the via hole and the conductor circuit 25 of a predetermined pattern are formed just above the conductive pillar 14 by etching in a pattern.
(FIG. 1H).

(2) After the substrate 30 was washed with water and dried, NaOH (10 g /
l), NaClO ₂ (40 g / l), Na ₃ O ₄ (6 g
/ L), NaOH (10 g / l), Na as a reducing bath
By oxidation-reduction treatment using BH ₄ (6 g / l), a roughened layer 26 is provided on the surfaces of the conductor layer 24 and the conductor circuit 25 as shown in FIG. (3) The raw material composition for preparing the resin filler C described above is mixed and kneaded to obtain a resin filler.

(4) Printing is performed on the core substrate 30 using a mask, and the filler 40 is applied to the surface of the substrate 30 (FIG. 2).
(J)). After that, the filler 40 is thermally cured.

(5) The substrate 30 after the processing of the above (4)
Is subjected to belt sanding using # 400 belt polishing paper (manufactured by Sankyo Rikagaku Co., Ltd.) to form the conductor layer 24
5 is polished so that no resin filler remains on the surface, and then buffing is performed with SiC abrasive grains to remove the scratches caused by the belt sander polishing. Such a series of polishing is similarly performed on the other surface of the substrate. Then 10
Heat treatment is performed at 0 ° C. for 1 hour and at 150 ° C. for 1 hour to cure the resin filler 40. Thus, the conductor layer 2
4 and the roughened layer on the upper surface of the conductor circuit 25 are removed, and the substrate 3
0 are smoothed as shown in FIG.

(6) As shown in FIG. 3 (L), on the upper surfaces of the conductor layers 24 and the conductor circuits 25 exposed in the process (5),
A roughened layer (concavo-convex layer) 42 made of a 2.5 μm thick Cu—Ni—P alloy is formed, and a 0.3 μm thick Sn layer (not shown) is provided on the surface of the roughened layer 42. . The formation method is as follows. The substrate 30 was acid-degreased and soft-etched, and then treated with a catalyst solution comprising palladium chloride and an organic acid to provide a Pd catalyst. After activating this catalyst, copper sulfate 8 g / l and nickel sulfate 0 .
6 g / l, citric acid 15 g / l, sodium hypophosphite 29 g / l, boric acid 31 g / l, surfactant 0.1 g / l
1, plating is performed in an electroless plating bath having a pH of 9 and a roughened layer 4 of Cu—Ni—P alloy is formed on the upper surface of the conductor circuit 24.
Form 2 Then, tin borofluoride 0.1 mol /
1, thiourea 1.0 mol / l, temperature 50 ° C., pH = 1.
A Cu—Sn substitution reaction is performed under the conditions of 2 to provide a 0.3 μm thick Sn layer on the surface of the roughened layer 42.

(7) The above-mentioned raw material composition for preparing the interlayer resin insulating material of the composition B was mixed by stirring, and the viscosity was 1.5 Pa · s.
To obtain an interlayer resin insulating agent (for lower layer). Then
The raw material composition for preparing the adhesive for electroless plating of the composition A described above is stirred and mixed to adjust the viscosity to 7 Pa · s to obtain an adhesive solution for electroless plating (for the upper layer).

(8) The substrate 30 of the above (6) (FIG. 3)
(L)), as shown in FIG.
The interlayer resin insulating agent (for lower layer) 44 having a viscosity of 1.5 Pa · s obtained in the above was applied by a roll coater within 24 hours after preparation, and left in a horizontal state for 20 minutes, and then dried at 60 ° C. for 30 minutes. (Pre-bake). Next, the photosensitive adhesive solution (for the upper layer) having a viscosity of 7 Pa · s obtained in the above (7) 4
6 is applied within 24 hours after preparation, left in a horizontal state for 20 minutes, and then dried (prebaked) at 60 ° C. for 30 minutes to form an adhesive layer 50 having a thickness of 35 μm.

(9) A photomask film (not shown) on which a black circle of 85 μmφ is printed is brought into close contact with both surfaces of the substrate 30 on which the adhesive layer 50 has been formed in the above (8), and 500 mJ / to exposure in cm ^2. This is DMTG
The substrate is exposed to 3000 mJ / cm ² by an ultra-high pressure mercury lamp, and subjected to a heat treatment (post-bake) at 100 ° C. for 1 hour, 120 ° C. for 1 hour, and then at 150 ° C. for 3 hours. As a result, as shown in FIG. 4 (N), an 85 μmφ opening (via hole forming opening) 4 having excellent dimensional accuracy corresponding to a photomask film.
35 having a thickness of 35 μm and having a thickness of 8 (two-layer structure)
Form 50. Note that the tin plating layer is partially exposed in the opening 48 serving as a via hole.

(10) The substrate 30 having the opening 48 formed
Is immersed in chromic acid for 19 minutes to dissolve and remove the epoxy resin particles present on the surface of the interlayer resin insulation layer 50, thereby forming the interlayer resin insulation layer 50 as shown in FIG.
Is made a roughened surface 51, and then immersed in a neutralizing solution (manufactured by Shipley) and then washed with water. Further, by applying a palladium catalyst (manufactured by Atotech) to the surface of the substrate 30 which has been subjected to the surface roughening treatment (roughening depth: 3 μm), the surface of the interlayer resin insulating layer 50 and the inner wall surface of the via hole opening 48 are formed. Attach catalyst core.

(11) The substrate is immersed in an aqueous electroless copper plating solution having the following composition to form an electroless copper plating film 52 having a thickness of 0.6 μm on the entire rough surface as shown in FIG. 4 (P). Form. [Electroless plating aqueous solution] EDTA 150 g / l Copper sulfate 20 g / l HCHO 30 ml / l NaOH 40 g / l α, α'-bipyridyl 80 mg / l PEG 0.1 g / l [Electroless plating conditions] 30 minutes at 70 ° C liquid temperature

(12) After attaching a commercially available resist film, a mask is placed and exposed at 100 mJ / cm ² .
After developing with 0.8% sodium carbonate, a plating resist 54 having a thickness of 15 μm is provided as shown in FIG.

(13) Next, electrolytic copper plating is performed under the same conditions as those for forming the above-mentioned conductive pillars to a thickness of 15 μm.
Is formed (FIG. 5 (R)).

(14) The plating resist 56 is made of 5% KO
After stripping and removing with H, the electroless plating film 52 under the plating resist 56 is dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide, and as shown in FIG. 52 and a thickness 15 composed of the electrolytic copper plating film 56
A conductor circuit 58 and a via hole 60 of μm are formed.
Further, the surface of the adhesive layer for electroless plating between the conductor circuit 58 and the via hole 60 is etched by 1 μm at 70 ° C. for 3 minutes in 800 g / l chromic acid to remove the palladium catalyst on the surface.

(15) Substrate 30 on which conductor circuit 58 is formed
Was prepared by adding 8 g / l of copper sulfate, 0.6 g / l of nickel sulfate, 15 g / l of citric acid, 29 g / l of sodium hypophosphite, 31 g / l of boric acid, and 0.1 g / l of a surfactant.
= 9, and a thickness of 3 mm was applied to the surfaces of the conductor circuit 58 and the via hole 60 as shown in FIG.
A roughened layer 62 of μm copper-nickel-phosphorus is formed. Then, Cu-Sn substitution reaction was carried out under the conditions of tin borofluoride 0.1 mol / l, thiourea 1.0 mol / l, temperature 50 ° C., pH = 1.2, and 0.3 μm was applied to the surface of the roughened layer 62.
A Sn layer having a thickness of μm is provided (the Sn layer is not shown).

(16) By repeating the steps (2) to (15), an upper interlayer resin insulation layer 150, a via hole 160 and a conductor circuit 158 are further formed (FIG. 6).
(U)).

(17) Then, as shown in FIG. 7, an opening 71 corresponding to the pad portion was provided (opening diameter 200 μm).
m) After the formation of the solder resist layer (thickness: 20 μm) 70, a resin composition for reinforcing the solder resist layer is applied around the opening group of the solder resist to form a reinforcement layer 78 having a thickness of 40 μm.

(18) Next, the substrate 30 is immersed in an electroless nickel plating solution for 20 minutes, so that the opening 71 has a thickness of 5 μm.
Then, a nickel plating layer 72 having a thickness of 0.03 μm is formed on the nickel plating layer by immersing the substrate 30 in an electroless gold plating solution.

(19) The solder resist layer 70
The solder paste is printed on the opening 71 of
Solder bumps 76U, 76D
Is formed, and a printed wiring board having a solder pump is manufactured.

In the method for manufacturing a multilayer printed wiring board according to the present embodiment, the via holes 60 are formed directly above the conductive pillars 14 of the core substrate 30, thereby eliminating the connection pads with the via holes on the surface of the core substrate 30. The conductive pillars 14 are arranged at a fine pitch to establish a vertical connection.

[0057]

According to the first and second aspects of the present invention, the conductor pillar having a function as a through-hole is fixed with resin, and the through-hole is not used. be able to.

According to the third aspect of the present invention, since the resin for fixing the conductor pillars is thermoplastic, the core substrate has good electrical characteristics such as a dielectric constant and can be used for a high-frequency multilayer printed wiring board.

In the method for manufacturing a core substrate according to the fourth and fifth aspects, since the conductive pillar is formed in the resist opening which can be formed to have a smaller diameter than the through hole formed by the drill used for forming the through hole, the opening having the small diameter is formed. By using the conductive pillars formed therein, the upper and lower connections can be made at a fine pitch.

In the method of manufacturing a core substrate according to the sixth aspect, since the conductive columns are formed by electrolytic plating, they can be formed inexpensively and quickly.

In the multilayer printed wiring board according to the present invention, the via hole is formed directly above the conductive pillar of the core substrate,
Eliminates pads and allows up and down connections with fine pitch.

[Brief description of the drawings]

1 (A), 1 (B), 1 (C), 1
(D) and FIG. 1 (E) are process diagrams of a method for manufacturing a core substrate according to one embodiment of the present invention.

2 (F), 2 (G), 2 (H), 2
(I) and FIG. 2 (J) are process diagrams of a method for manufacturing a multilayer printed wiring board according to one embodiment of the present invention.

3 (K), 3 (L) and 3 (M) are process diagrams of a method for manufacturing a multilayer printed wiring board according to one embodiment of the present invention.

FIGS. 4 (N), 4 (O), and 4 (P) are process diagrams of a method for manufacturing a multilayer printed wiring board according to one embodiment of the present invention.

FIGS. 5 (Q), 5 (R), and 5 (S) are process diagrams of a method for manufacturing a multilayer printed wiring board according to one embodiment of the present invention.

FIGS. 6 (T) and 6 (U) are process diagrams of a method for manufacturing a multilayer printed wiring board according to one embodiment of the present invention.

FIG. 7 is a cross-sectional view of a method for manufacturing a multilayer printed wiring board according to one embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Copper foil (conductor) 12 Resist 12a Opening 14 Conductive pillar 16 Resin 24 Conductor circuit 30 Core substrate 50 Interlayer resin insulation layer 56 Electroless plating copper film 58 Conductor circuit 60 Via hole

Claims (7)

[Claims] 1. A core substrate for a multilayer printed wiring board, wherein a conductive pillar is fixed with a resin. 2. The core substrate according to claim 1, wherein the diameter of the conductive pillar is not more than 0.25 mm and not less than 0.05 mm. 3. The core substrate according to claim 1, wherein the resin is a thermoplastic resin. 4. A method for manufacturing a core substrate for a multilayer printed wiring board, comprising the following steps (a) to (d). (A) forming a resist having an opening on a conductor, (b) forming a conductive column by plating the opening, (c) removing the resist, and (d) between the conductive columns. The step of filling the resin. 5. A method of manufacturing a core substrate for a multilayer printed wiring board, comprising the following steps (a) to (e). (A) forming a resist having an opening on a conductor, (b) forming a conductive column by plating the opening, (c) removing the resist, and (d) between the conductive columns. The step of filling the resin. (E) polishing the upper portion of the filled resin to expose the conductive columns. 6. The method according to claim 4, wherein in the step of forming the conductive pillar by plating, the conductive pillar is formed by electrolytic plating. 7. A multilayer printed wiring board in which interlayer resin insulating layers, via holes, and conductive circuits are alternately laminated on a core substrate, wherein the core substrate has conductive pillars fixed with resin. A multilayer printed wiring board, wherein the via hole is formed immediately above the conductive pillar of a core substrate.