JPH117309A - Programmable controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correctly grasp a pipeline operation from an external part by providing a control means for storing the addresses of instructions to be pipeline-processed for address registers which are provided in accordance with the respective stages of pipelines. SOLUTION: A controlblock 19 is the one for controlling a whole gate array 10 and incorporates UMA registers 1-4. The addresses of programs to be executed in the respective pipelines are preserved in the UMA registers 1-4. The contents of the addresses of the UMA registers are controlled based on a control signal so that the address of an instruction word under execution is written in the UMA register 1 and the address of the instruction word to be execrated next is written in the UMA register 2. Therefore, the contents (addresses) of the UMA registers 1 and 2 are referred to by CPUs 31 and 32 so that the instruction under execution at present and the instruction to be executed next are grasped.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a programmable controller, and more particularly to an address of an instruction to be pipelined.

[0002]

2. Description of the Related Art Conventionally, there is a programmable controller using a pipeline structure. Normally, the execution of an instruction by the pipeline structure is basically executed by one instruction in one cycle. However, when each instruction performs a complicated operation, it may take many cycles to execute the instruction. In that case, it is necessary to suspend a part of the pipeline by that much, and as a result, the turbulence of the pipeline becomes large.
This occurs in most instruction execution units using a pipeline structure, in which case there is no need to pause the pipeline. ).

[0003]

However, no matter how disturbed the pipeline is, the external CPU must be able to accurately grasp the pipeline operation. There are at least two reasons for this. a) The programmable controller has an interrupt function. When an external interrupt is sent to the programmable controller, the programmable controller immediately interrupts the program being executed and executes the interrupt program. is there.
However, when the execution of the interrupt program ends, the execution of the interrupted program must be resumed, and for that purpose, the external CPU needs to accurately grasp the address being executed. b) One of the functions of the programmable controller is a debug function, which executes instructions one by one according to an instruction of an operator. In order to realize this function, it is necessary that the address being executed by the external CPU be accurately grasped and fed back to the operator. However, in the conventional programmable controller, when the pipeline is disturbed, the external CPU cannot accurately grasp the operation of the pipeline, which causes a problem.

[0004] The present invention has been made to solve such a problem, and an object of the present invention is to provide a programmable controller capable of accurately grasping a pipeline operation from an external CPU.

[0005]

SUMMARY OF THE INVENTION A programmable controller according to the present invention includes an arithmetic means for performing a predetermined number of stages of pipeline processing as internal processing, and an address register provided corresponding to each stage of the pipeline. Control means for generating a control signal corresponding to the line processing and storing the address of the instruction to be pipeline-processed in the address register, wherein the address register stores at least the address of the instruction currently being executed. Thus, the command currently being executed can be grasped from an external CPU or the like.

[0006]

FIG. 1 is a block diagram showing a configuration of a gate array of a programmable controller according to an embodiment of the present invention. In FIG. 1, reference numeral 10 denotes a gate array, and reference numerals 11 to 19 denote functional blocks included in the gate array 10, respectively. Reference numeral 11 denotes a CPU interface block, which comprises a gate array 10 and an external CP.
It is to interface with U31, U32.
Reference numeral 12 denotes a trap circuit block, which traps a UM (user memory) address. 13 is U
M memory interface block, which is UM
The user program is exchanged with the memory 41. 1
Reference numeral 4 denotes an MM memory interface block which exchanges microcode with the MM memory 42.
Reference numeral 15 denotes a VM memory interface block, which exchanges status and data with the VM memory 43. An instruction decode block 16 analyzes an instruction word and generates a microcode address corresponding to the analysis result. Reference numeral 17 denotes an instruction execution block, which executes an instruction based on microcode.
Reference numeral 18 denotes an arithmetic circuit block which performs arithmetic processing. Reference numeral 19 denotes a control block, which controls the entire gate array 10 and includes UMA registers 1 to 4. The UMA register 1 to the UMA register 4 store addresses of programs executed in the respective pipelines.

FIG. 2 is an explanatory diagram of a cycle of the pipeline processing of the gate array 10 of FIG. As shown in the figure, in cycle 1, an instruction word is read from the UM memory 41 by the UM memory interface block 13, in cycle 2 the instruction word is decoded by the instruction decode block 16, and in cycle 3, the MM memory interface block 14 The microcode corresponding to the decoded instruction word is read from the MM memory 42, and in cycle 4, the instruction execution block 17 executes an instruction based on the microcode.

FIG. 3 is an explanatory diagram showing an example of instruction execution by pipeline processing. In the illustrated example, the execution of the instruction is completed in one cycle.

FIG. 4 is an explanatory diagram showing another example of instruction execution by pipeline processing. In the example shown, 3
The execution of the instruction is completed in the cycle, and the first and second pipelines are put on standby (WAIT) until the execution of the instruction is completed, and the third and fourth pipelines are waited for. Only the line is operating.

FIG. 5 is an explanatory diagram showing still another example of instruction execution by pipeline processing. In the illustrated example, the execution of the CALL instruction or the like causes a branch process in the user program. In this case, the first and second pipelines are connected to the third and fourth pipelines. Independent from the stage, and each is operated separately. That is,
The first stage wait (WAIT) and the second stage wait (WAI)
T) are sequentially released.

FIG. 6 is an explanatory diagram showing an operation state in which the state of the pipeline in the control block 19 is defined. In order to secure the stable operation of the gate array 10, it is necessary to define the operation state of the entire circuit in advance. In the present embodiment, the control block 19 defines five operation states based on the pipeline state. ing. Five modes, a CPU mode, an instruction execution mode 1, an instruction execution mode 2, an instruction execution mode 3, and an instruction execution mode 4, are defined. The CPU mode is started by a power-on and a break instruction or an END instruction in the instruction execution mode 4.
The processing is started by a program execution start command from the PUs 31 and 32, and the first stage pipeline is used. In each of the instruction execution mode 2 to the instruction execution mode 4, the processing starts when the previous mode ends. The instruction execution mode 2 uses the first and second stage pipelines, and the instruction execution mode 3 uses the first to third stage pipelines. In the instruction execution mode 4, the first to fourth pipeline stages are used, and the instruction execution mode 4 is continued until a break instruction or an END instruction appears.

The following addresses are stored in the UMA registers 1 to 4 incorporated in the control block 19 of FIG. UMA register 1: Saves the currently executed or executed address (in CPU mode). UMA register 2: Stores the address to be executed next. UMA register 3: Saves the next address to be executed. UMA register 4: Stores the address being read from the UM memory 41.

Table 1 is a table showing the relationship between data (address) stored in the UMA registers 1 to 4 and control signals.

[0014]

[Table 1]

The control signals shown in Table 1 are turned on in the following states. GCST1: ON when the state is the instruction execution mode 1 GCST2: ON when the state is the instruction execution mode 2 GCST3: ON when the state is the instruction execution mode 3 MDGCCE: O when the processing of one instruction word is completed
N MDGCSFFT: ON when register shift instruction is given by microcode MDGCEND: ON when END instruction is executed

Next, the relationship between the control signal, the pipeline processing, and the address of the UMA register will be described. Here, the address of the instruction word 1 is A, and the instruction word 2 is
Is B, the address of instruction 3 is C, the address of instruction 4 is D, the address of instruction 5 is E, the address of instruction 6 is F, the address of instruction 7 is G, and the address of instruction 8 is Is H, and the address of the instruction word 9 is I.

FIG. 7 is a diagram showing a transition state of the address of the UMA register corresponding to the pipeline processing of FIG. 3, and shows a case where an instruction is completed every cycle. In the cycle 1, the instruction word 1 is read, so that the address “A” for reading the instruction word 1 from the UM memory 41 is written to the UMA register 4. Since the cycle 1 is the instruction execution mode 1, the GCST 1 is executed at the time when the cycle 1 is completed (to be precise, slightly before the time when the cycle 1 is completed. This is the same in the case described later). It turns ON, and the data (address) enabled in the UMA register 2 is written to the UMA registers 1 and 3. Note that U
In this example, "A" is stored in the MA register 2 in the initial state.
“3” is written in “3”. Also, UMA
An address “B” for reading the next instruction word 2 is written in the register 4.

Next, in cycle 2, the instruction word 2 is read and the instruction word 1 is decoded. Cycle 2
Is in instruction execution mode 2, so GC
ST2 turns ON, and the contents of UMA register 4 are
Write to register 3 and in a similar manner UMA register 3
The addresses stored in the UMA registers 4-1 are simultaneously shifted, such as → UMA register 2, UMA register 2 → UMA register 1, and so on. And cycle 3
Is in the instruction execution mode 3, the GCST3 is turned on at the end of the instruction execution, and similarly, the addresses stored in the UMA registers 4-1 are simultaneously shifted.
In the cycle 4, the processing of the instruction word 1 is completed, so that MDGCCE is turned on at the time of the completion, and the UMA registers 4 to 1 are processed in the same manner as described above.
At the same time. Therefore,
The addresses of UMA register 4 to UMA register 1 in cycle 5 are as shown in FIG.
"E", "D", "C", "B". Also in cycle 5, in this example, the processing of instruction word 2 ends, so that MDGCCE is turned on at the end of cycle 5.
And the addresses stored in the UMA registers 4-1 are simultaneously shifted and rewritten.

FIG. 8 is a diagram showing a transition state of the address of the UMA register corresponding to the pipeline processing of FIG. 4. Here, a case where an instruction is completed in three cycles is shown. Cycles 1 to 3 are the same as those in FIG. 7, but in this example, the instruction is not completed in cycle 4 and the instruction is completed in cycle 6, so the UMA registers 4-1 are not used in cycles 4 to 6. Hold the same address. Then, at the end of cycle 6, MDGCCE turns ON, and U
The addresses stored in the MA registers 4-1 are simultaneously shifted and rewritten.

FIG. 9 is a diagram showing a transition state of the address of the UMA register corresponding to the pipeline processing of FIG. 5, and shows a case where a branch processing occurs during execution of an instruction. At the end of the cycle 5 in which the branch processing has occurred and the instruction word 6 has been read, and at the end of the next cycle 6, MDGCSHHT is turned ON, and the contents of the UMA register 1 are maintained as they are. The contents are simultaneously shifted and rewritten.

As apparent from FIGS. 7 to 9, the control signals GCST1 to GCST1, MDGCCE, MDG
By controlling the contents of the address of the UMA register based on CSFT and MDGCEND, the UMA register 1 stores the instruction being executed (or the executed instruction (CP
The address of the instruction word to be executed next is written in the UMA register 2 in the U mode register 2). Therefore, the CPUs 31 and 32 in FIG.
By referring to the contents (address) of the registers 1 and 2,
It is possible to grasp the instruction currently being executed (or the executed instruction word) and the instruction to be executed next.

[0022]

As described above, according to the present invention, the operation means for performing the pipeline processing and the address register provided corresponding to each stage of the pipeline, and the control signal corresponding to the pipeline processing is provided. Control means for generating and storing the address of the instruction to be pipelined in the address register, and storing at least the address of the currently executing instruction in the address register. The address of the instruction word can be accurately grasped, and therefore, the content of the instruction can be grasped.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a gate array of a programmable controller according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a cycle of pipeline processing of the gate array of FIG. 1;

FIG. 3 is an explanatory diagram showing an example of instruction execution by pipeline processing.

FIG. 4 is an explanatory diagram showing another example of instruction execution by pipeline processing.

FIG. 5 is an explanatory diagram showing still another example of instruction execution by pipeline processing.

FIG. 6 is an explanatory diagram showing an operation state that defines a pipeline state in the control block of FIG. 1;

7 is a diagram showing a transition state of an address of a UMA register corresponding to the pipeline processing of FIG. 3;

FIG. 8 is a diagram showing a transition state of an address of a UMA register corresponding to the pipeline processing of FIG. 4;

FIG. 9 is a diagram showing a transition state of an address of a UMA register corresponding to the pipeline processing of FIG. 5;

Claims (1)

[Claims] 1. An arithmetic unit for performing a predetermined number of stages of pipeline processing as internal processing, and an address register provided for each stage of the pipeline to generate a control signal corresponding to the pipeline processing. Control means for storing an address of an instruction to be pipeline-processed in the address register, wherein at least an address of an instruction currently being executed is stored in the address register.