JPS5267554A - Phase synchronous circuit - Google Patents

Phase synchronous circuit

Info

Publication number
JPS5267554A
JPS5267554A JP50144265A JP14426575A JPS5267554A JP S5267554 A JPS5267554 A JP S5267554A JP 50144265 A JP50144265 A JP 50144265A JP 14426575 A JP14426575 A JP 14426575A JP S5267554 A JPS5267554 A JP S5267554A
Authority
JP
Japan
Prior art keywords
phase synchronous
synchronous circuit
phase
circuit
simplifieed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP50144265A
Other languages
Japanese (ja)
Other versions
JPS5740682B2 (en
Inventor
Yasutsune Yoshida
Yoshimi Tagashira
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP50144265A priority Critical patent/JPS5267554A/en
Priority to US05/743,910 priority patent/US4109102A/en
Priority to DE2654276A priority patent/DE2654276C3/en
Priority to IT30013/76A priority patent/IT1064807B/en
Publication of JPS5267554A publication Critical patent/JPS5267554A/en
Publication of JPS5740682B2 publication Critical patent/JPS5740682B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE: To effectively make the base band process by the simplifieed circuit constitution, by installing the phase apparatus to be shifted by π/8n, consisting of the attenautor and the adder or the subtracter, in the 4n phase synchronious circuit.
COPYRIGHT: (C)1977,JPO&Japio
JP50144265A 1975-12-02 1975-12-02 Phase synchronous circuit Granted JPS5267554A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP50144265A JPS5267554A (en) 1975-12-02 1975-12-02 Phase synchronous circuit
US05/743,910 US4109102A (en) 1975-12-02 1976-11-22 Phase synchronizing circuit
DE2654276A DE2654276C3 (en) 1975-12-02 1976-11-30 Phase-locking circuit arrangement
IT30013/76A IT1064807B (en) 1975-12-02 1976-12-01 PHASE SYNCHRONIZATION CIRCUIT

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50144265A JPS5267554A (en) 1975-12-02 1975-12-02 Phase synchronous circuit

Publications (2)

Publication Number Publication Date
JPS5267554A true JPS5267554A (en) 1977-06-04
JPS5740682B2 JPS5740682B2 (en) 1982-08-30

Family

ID=15358062

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50144265A Granted JPS5267554A (en) 1975-12-02 1975-12-02 Phase synchronous circuit

Country Status (1)

Country Link
JP (1) JPS5267554A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5146863A (en) * 1974-10-19 1976-04-21 Fujitsu Ltd

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5146863A (en) * 1974-10-19 1976-04-21 Fujitsu Ltd

Also Published As

Publication number Publication date
JPS5740682B2 (en) 1982-08-30

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