JPS5478679A - Complementary memory cell capable of electric erasion - Google Patents

Complementary memory cell capable of electric erasion

Info

Publication number
JPS5478679A
JPS5478679A JP14591977A JP14591977A JPS5478679A JP S5478679 A JPS5478679 A JP S5478679A JP 14591977 A JP14591977 A JP 14591977A JP 14591977 A JP14591977 A JP 14591977A JP S5478679 A JPS5478679 A JP S5478679A
Authority
JP
Japan
Prior art keywords
gate
memory cell
type
floating gate
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14591977A
Other languages
Japanese (ja)
Inventor
Hitoshi Kusano
Yoshiji Takabayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14591977A priority Critical patent/JPS5478679A/en
Publication of JPS5478679A publication Critical patent/JPS5478679A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To obtain a ROM cell which features reduced power consumption and is capable of both writing and erasing, by forming the complementary memory cell on the semiconductor substrate, providing the floating gate into the SiO2 film covering the memory cell and selecting the positive or negative electrification for the floating gate. CONSTITUTION:N-type region 11 is formed through diffusion on P-type semiconductor substrate 10, and P<+>-type source and drain regions 12 and 13 are formed within region 11. At the same time, N<+>-type source and drain regions 14 and 15 are formed at other regions of substrate 10. Then SiO2 film 18 is coated on the entire surface, and floating gate 16 composed of poly-crystal Si or metal along with control gate 17 are buried into film 18. Terminals T1-T7 are attached to each region except for gate 16. Thus, the ROM cell is formed, and gate 16 is electrified positive or negative. As a result, both the writing and erasing actions can be ensured in a simple way. Furthermore, the power consumption is reduced greatly because of the complementary type.
JP14591977A 1977-12-05 1977-12-05 Complementary memory cell capable of electric erasion Pending JPS5478679A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14591977A JPS5478679A (en) 1977-12-05 1977-12-05 Complementary memory cell capable of electric erasion

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14591977A JPS5478679A (en) 1977-12-05 1977-12-05 Complementary memory cell capable of electric erasion

Publications (1)

Publication Number Publication Date
JPS5478679A true JPS5478679A (en) 1979-06-22

Family

ID=15396104

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14591977A Pending JPS5478679A (en) 1977-12-05 1977-12-05 Complementary memory cell capable of electric erasion

Country Status (1)

Country Link
JP (1) JPS5478679A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2534091A1 (en) * 1982-09-30 1984-04-06 Rca Corp PROGRAMMABLE AND ELECTRICALLY DELETED ROCKER
US4686558A (en) * 1982-09-15 1987-08-11 Itt Industries, Inc. CMOS memory cell having an electrically floating storage gate
US4785199A (en) * 1983-11-28 1988-11-15 Stanford University Programmable complementary transistors
JP2009239161A (en) * 2008-03-28 2009-10-15 Genusion Inc Nonvolatile semiconductor memory device and usage method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4686558A (en) * 1982-09-15 1987-08-11 Itt Industries, Inc. CMOS memory cell having an electrically floating storage gate
FR2534091A1 (en) * 1982-09-30 1984-04-06 Rca Corp PROGRAMMABLE AND ELECTRICALLY DELETED ROCKER
US4785199A (en) * 1983-11-28 1988-11-15 Stanford University Programmable complementary transistors
JP2009239161A (en) * 2008-03-28 2009-10-15 Genusion Inc Nonvolatile semiconductor memory device and usage method thereof

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