JPS55129999A - Data memory protection circuit - Google Patents

Data memory protection circuit

Info

Publication number
JPS55129999A
JPS55129999A JP3648979A JP3648979A JPS55129999A JP S55129999 A JPS55129999 A JP S55129999A JP 3648979 A JP3648979 A JP 3648979A JP 3648979 A JP3648979 A JP 3648979A JP S55129999 A JPS55129999 A JP S55129999A
Authority
JP
Japan
Prior art keywords
data memory
noise
write
write enable
control unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3648979A
Other languages
Japanese (ja)
Other versions
JPS6231384B2 (en
Inventor
Mitsuo Suzuki
Tadashi Nakanishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3648979A priority Critical patent/JPS55129999A/en
Publication of JPS55129999A publication Critical patent/JPS55129999A/en
Publication of JPS6231384B2 publication Critical patent/JPS6231384B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Storage Device Security (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
  • Exchange Systems With Centralized Control (AREA)

Abstract

PURPOSE: To make it possible to protect system data in the data memory by making it possible to discriminate noise from the external and signals and by preventing the data memory from being the write enable state due to noise.
CONSTITUTION: If alternate repeat of the set signal and the reset signal inputted from a central control unit to FF223 through terminals 200 and 201 is a trigger period or more consisting of the time constant of the circuit constituted by resistance 210 of monostable multivibrator 224 and capacitor 213, outputted pulses are decided as pulses caused by noise, etc. Then, output terminal Q' of monostable multivibrator 224 becomes H-level, and counter 228 stops counting immediately without counting of outputted pluses. Therefore, data memory 220 is prevented from being the write enable state due to noise, etc. Further, if no write signal is inputted from the central control unit within a fixed time after write enable FF222 is set once, memory 220 is set to the write disable state also.
COPYRIGHT: (C)1980,JPO&Japio
JP3648979A 1979-03-28 1979-03-28 Data memory protection circuit Granted JPS55129999A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3648979A JPS55129999A (en) 1979-03-28 1979-03-28 Data memory protection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3648979A JPS55129999A (en) 1979-03-28 1979-03-28 Data memory protection circuit

Publications (2)

Publication Number Publication Date
JPS55129999A true JPS55129999A (en) 1980-10-08
JPS6231384B2 JPS6231384B2 (en) 1987-07-08

Family

ID=12471229

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3648979A Granted JPS55129999A (en) 1979-03-28 1979-03-28 Data memory protection circuit

Country Status (1)

Country Link
JP (1) JPS55129999A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6133556A (en) * 1984-07-25 1986-02-17 Fujitsu Ltd Protecting method of writing in memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6133556A (en) * 1984-07-25 1986-02-17 Fujitsu Ltd Protecting method of writing in memory

Also Published As

Publication number Publication date
JPS6231384B2 (en) 1987-07-08

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