JPS55165661A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS55165661A
JPS55165661A JP7371879A JP7371879A JPS55165661A JP S55165661 A JPS55165661 A JP S55165661A JP 7371879 A JP7371879 A JP 7371879A JP 7371879 A JP7371879 A JP 7371879A JP S55165661 A JPS55165661 A JP S55165661A
Authority
JP
Japan
Prior art keywords
pads
elements
packages
semiconductor
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7371879A
Other languages
Japanese (ja)
Other versions
JPS614189B2 (en
Inventor
Norio Honda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7371879A priority Critical patent/JPS55165661A/en
Publication of JPS55165661A publication Critical patent/JPS55165661A/en
Publication of JPS614189B2 publication Critical patent/JPS614189B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/6875—Shapes or dispositions thereof being on a metallic substrate, e.g. insulated metal substrates [IMS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce the number of parts and cost, by connecting semiconductor elements with terminal pads and attaching the elements to a terminal board having external leads at prescribed intervals, in stacking the semiconductor elements. CONSTITUTION:Semiconductor memory elements 1 for an ROM, an RAM or the like are housed in ceramic packages 6. The electrodes of the elements are connected by thin wires 7 to bonding pads 8 provided in the packages 6. The pads 8 are connected through electroconductive layers 9 to terminal pads 10, 10' provided on both the obverse and reverse sides of the packages. A seal-up lid 6' is fitted on the open end of each package. Separate semiconductor memories 5 are thus manufactured. These memories are stacked by using solder 4. The lowest memory 5 is attached by solder 4' to a terminal board 11 which has external leads 2, carrier pads 13 and electroconductive layers 14 so that a stack-structured device is provided. According to this constitution, assembly is simplified and cost is reduced.
JP7371879A 1979-06-12 1979-06-12 Semiconductor device Granted JPS55165661A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7371879A JPS55165661A (en) 1979-06-12 1979-06-12 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7371879A JPS55165661A (en) 1979-06-12 1979-06-12 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS55165661A true JPS55165661A (en) 1980-12-24
JPS614189B2 JPS614189B2 (en) 1986-02-07

Family

ID=13526275

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7371879A Granted JPS55165661A (en) 1979-06-12 1979-06-12 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS55165661A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59136963A (en) * 1983-01-25 1984-08-06 Sanyo Electric Co Ltd Multilayer mounting structure of memory storage
JPH0613540A (en) * 1991-12-03 1994-01-21 Nec Corp Multi-chip module
US5299092A (en) * 1991-05-23 1994-03-29 Hitachi, Ltd. Plastic sealed type semiconductor apparatus
US5381039A (en) * 1993-02-01 1995-01-10 Motorola, Inc. Hermetic semiconductor device having jumper leads
KR100238197B1 (en) * 1992-12-15 2000-01-15 윤종용 Semiconductor device
KR100253325B1 (en) * 1997-09-27 2000-04-15 김영환 Land grid array package and fabricating method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59136963A (en) * 1983-01-25 1984-08-06 Sanyo Electric Co Ltd Multilayer mounting structure of memory storage
US5299092A (en) * 1991-05-23 1994-03-29 Hitachi, Ltd. Plastic sealed type semiconductor apparatus
JPH0613540A (en) * 1991-12-03 1994-01-21 Nec Corp Multi-chip module
KR100238197B1 (en) * 1992-12-15 2000-01-15 윤종용 Semiconductor device
US5381039A (en) * 1993-02-01 1995-01-10 Motorola, Inc. Hermetic semiconductor device having jumper leads
KR100253325B1 (en) * 1997-09-27 2000-04-15 김영환 Land grid array package and fabricating method thereof

Also Published As

Publication number Publication date
JPS614189B2 (en) 1986-02-07

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