JPS5538609A - Error recovery processing system for read-only memory - Google Patents

Error recovery processing system for read-only memory

Info

Publication number
JPS5538609A
JPS5538609A JP10878978A JP10878978A JPS5538609A JP S5538609 A JPS5538609 A JP S5538609A JP 10878978 A JP10878978 A JP 10878978A JP 10878978 A JP10878978 A JP 10878978A JP S5538609 A JPS5538609 A JP S5538609A
Authority
JP
Japan
Prior art keywords
read
circuit
microinstruction
unit
request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10878978A
Other languages
Japanese (ja)
Inventor
Toru Koshiba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10878978A priority Critical patent/JPS5538609A/en
Publication of JPS5538609A publication Critical patent/JPS5538609A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)

Abstract

PURPOSE: To improve the reliability of an error recovery process by using a copy data in a main memory unit and small-scale hardware for a read-data bit error of a read-only memory.
CONSTITUTION: When microinstruction read control circuit 2 detects a multi-bit error in a microinstruction read out from read-only memory unit 1, multi-bit error display signal 2' is supplied from circuit 2 to request generating circuit 5. On receiving signal 2', circuit 5 requests main memory control unit 6 to generate a data read request to main memory unit 10. At this time, a corresponding read-only address from address control circuit 3 to circuit 5, where it is converted into address (a) in unit 10 before being transferred together with a request to read. Corresponding to the request to read supplied from 6 to unit 10, a microinstruction is read out and sent to circuit 2, which interprets a supplied microinstruction data bit pattern to control the execution.
COPYRIGHT: (C)1980,JPO&Japio
JP10878978A 1978-09-04 1978-09-04 Error recovery processing system for read-only memory Pending JPS5538609A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10878978A JPS5538609A (en) 1978-09-04 1978-09-04 Error recovery processing system for read-only memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10878978A JPS5538609A (en) 1978-09-04 1978-09-04 Error recovery processing system for read-only memory

Publications (1)

Publication Number Publication Date
JPS5538609A true JPS5538609A (en) 1980-03-18

Family

ID=14493512

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10878978A Pending JPS5538609A (en) 1978-09-04 1978-09-04 Error recovery processing system for read-only memory

Country Status (1)

Country Link
JP (1) JPS5538609A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5023742A (en) * 1973-06-13 1975-03-14
JPS52125242A (en) * 1976-04-14 1977-10-20 Nec Corp Multiple control memory unit
JPS5395532A (en) * 1977-02-01 1978-08-21 Nec Corp Error correction system for read only memory unit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5023742A (en) * 1973-06-13 1975-03-14
JPS52125242A (en) * 1976-04-14 1977-10-20 Nec Corp Multiple control memory unit
JPS5395532A (en) * 1977-02-01 1978-08-21 Nec Corp Error correction system for read only memory unit

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