JPS5542347A - Pcm signal recording system - Google Patents

Pcm signal recording system

Info

Publication number
JPS5542347A
JPS5542347A JP11551678A JP11551678A JPS5542347A JP S5542347 A JPS5542347 A JP S5542347A JP 11551678 A JP11551678 A JP 11551678A JP 11551678 A JP11551678 A JP 11551678A JP S5542347 A JPS5542347 A JP S5542347A
Authority
JP
Japan
Prior art keywords
data
taps
memory
sequentially
correction words
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11551678A
Other languages
Japanese (ja)
Inventor
Hiromi Juso
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP11551678A priority Critical patent/JPS5542347A/en
Publication of JPS5542347A publication Critical patent/JPS5542347A/en
Pending legal-status Critical Current

Links

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  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Error Detection And Correction (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)

Abstract

PURPOSE: To improve error correction performance by adding more than two error- correction words different in logical combination to data in each period.
CONSTITUTION: Delay circuit 33 has taps 34W35 for extracting data delayed after delay values E, 2E... and taps 36W37 for data delayed after delay values D, 2D.... Now at the point in time when digitized right and left data L1 and R1, L2 and R2, and L3 and R3 from A/D converter 30 are sequentially stored in memory 32, data of taps 34W35, and 36W37 are ORed by logic circuits 38 and 39 respectively. Then their outputs are used as correction words P and Q, which are stored in memory 32 by switching switch 40 at the end of data, i.e., after R3 sequentially. Then, next data L4, R4... are transmitted to memory 32. Repetition of these operations add correction words P and Q sequentially. The PCM signal record in this way can be corrected nearly completely by correction words P and Q even if an error occurs in generating.
COPYRIGHT: (C)1980,JPO&Japio
JP11551678A 1978-09-18 1978-09-18 Pcm signal recording system Pending JPS5542347A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11551678A JPS5542347A (en) 1978-09-18 1978-09-18 Pcm signal recording system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11551678A JPS5542347A (en) 1978-09-18 1978-09-18 Pcm signal recording system

Publications (1)

Publication Number Publication Date
JPS5542347A true JPS5542347A (en) 1980-03-25

Family

ID=14664450

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11551678A Pending JPS5542347A (en) 1978-09-18 1978-09-18 Pcm signal recording system

Country Status (1)

Country Link
JP (1) JPS5542347A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56124108A (en) * 1980-02-29 1981-09-29 Matsushita Electric Ind Co Ltd Digital signal recording system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56124108A (en) * 1980-02-29 1981-09-29 Matsushita Electric Ind Co Ltd Digital signal recording system

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