JPS5561850A - Computer system - Google Patents

Computer system

Info

Publication number
JPS5561850A
JPS5561850A JP13427778A JP13427778A JPS5561850A JP S5561850 A JPS5561850 A JP S5561850A JP 13427778 A JP13427778 A JP 13427778A JP 13427778 A JP13427778 A JP 13427778A JP S5561850 A JPS5561850 A JP S5561850A
Authority
JP
Japan
Prior art keywords
unit
control
execution
sentence
program
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13427778A
Other languages
Japanese (ja)
Inventor
Masaru Takesue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP13427778A priority Critical patent/JPS5561850A/en
Publication of JPS5561850A publication Critical patent/JPS5561850A/en
Pending legal-status Critical Current

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  • Devices For Executing Special Programs (AREA)

Abstract

PURPOSE: To speed up the program execution speed, by providing the unit executing the control sentence parallelly, other than the processor.
CONSTITUTION: In executing the program, first, the control sentence and operation sentence of a program are loaded as a bundle to the control sentence execution unit 4 to execute the control sentence. In encountering the execution of the operation sentence, the unit 4 transfers the types of operation and the operand address to the operation unit 3 to instruct the execution. when the unit 3 receives the instruction, the unit 2 is accessed according to the operand address, and the operation is executed by obtaining the operand, and after writing in the result to the unit 2 as required, the end report is made to the unit 4. The unit 4 restarts the execution of the control stream based on the result. In case of the presence of a plurality of control streams parallelly, the unit 4 instructs the operation belonging to one control stream to the unit 3 and other control stream is succeeded while the execution of the control stream is interrupted.
COPYRIGHT: (C)1980,JPO&Japio
JP13427778A 1978-10-31 1978-10-31 Computer system Pending JPS5561850A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13427778A JPS5561850A (en) 1978-10-31 1978-10-31 Computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13427778A JPS5561850A (en) 1978-10-31 1978-10-31 Computer system

Publications (1)

Publication Number Publication Date
JPS5561850A true JPS5561850A (en) 1980-05-09

Family

ID=15124512

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13427778A Pending JPS5561850A (en) 1978-10-31 1978-10-31 Computer system

Country Status (1)

Country Link
JP (1) JPS5561850A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49122941A (en) * 1973-03-26 1974-11-25
JPS51139225A (en) * 1975-02-15 1976-12-01 Mathematik & Datenverarbeitung Computer
JPS5334439A (en) * 1976-09-07 1978-03-31 Massachusetts Inst Technology Digital data processor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49122941A (en) * 1973-03-26 1974-11-25
JPS51139225A (en) * 1975-02-15 1976-12-01 Mathematik & Datenverarbeitung Computer
JPS5334439A (en) * 1976-09-07 1978-03-31 Massachusetts Inst Technology Digital data processor

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