JPS5567159A - Preparation of semiconductor integrated circuit - Google Patents

Preparation of semiconductor integrated circuit

Info

Publication number
JPS5567159A
JPS5567159A JP13982878A JP13982878A JPS5567159A JP S5567159 A JPS5567159 A JP S5567159A JP 13982878 A JP13982878 A JP 13982878A JP 13982878 A JP13982878 A JP 13982878A JP S5567159 A JPS5567159 A JP S5567159A
Authority
JP
Japan
Prior art keywords
poly
layer
films
wiring
constitution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13982878A
Other languages
Japanese (ja)
Inventor
Koichi Kanzaki
Akihiko Furukawa
Minoru Taguchi
Hajime Sasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13982878A priority Critical patent/JPS5567159A/en
Publication of JPS5567159A publication Critical patent/JPS5567159A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H10D84/0116—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs the components including integrated injection logic [I2L]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Logic Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

PURPOSE:To improve an integrating degree, by using poly Si as a diffusion source forming a collector layer of an I<2>L, and by insulating and separating the electrodes of the poly Si by selectively oxidizing the poly Si. CONSTITUTION:An n<+> buried layer 2 and an n epitaxial layer 3 are manufactured on a p-type Si substrate 1, p-type layers 4, 5 are mounted and these layers are coated with an oxide film 7. Holes are selectively opened on the layer 4, poly Si is diffused from a doped poly Si layer 10 and n<+>-type layers 6 are produced. Nitriding films 11 are installed at fixed locations, and an oxide film 12 is made up. Connecting holes 31 are choicely built up to the oxide films 7, 12, and Al wiring 9 is prepared. In this case, the poly Si films 10 and the Al wiring 9 directly contact. Since portions where poly Si is not needed are changed into poly Si oxide films 12 by selective oxidation according to this constitution, an integrating degree is high and an I<2>L can be formed as compared to a conventional etching removing method.
JP13982878A 1978-11-15 1978-11-15 Preparation of semiconductor integrated circuit Pending JPS5567159A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13982878A JPS5567159A (en) 1978-11-15 1978-11-15 Preparation of semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13982878A JPS5567159A (en) 1978-11-15 1978-11-15 Preparation of semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS5567159A true JPS5567159A (en) 1980-05-21

Family

ID=15254420

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13982878A Pending JPS5567159A (en) 1978-11-15 1978-11-15 Preparation of semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS5567159A (en)

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