JPS5573164A - Synchronous demodulation system of msk signal - Google Patents
Synchronous demodulation system of msk signalInfo
- Publication number
- JPS5573164A JPS5573164A JP14537178A JP14537178A JPS5573164A JP S5573164 A JPS5573164 A JP S5573164A JP 14537178 A JP14537178 A JP 14537178A JP 14537178 A JP14537178 A JP 14537178A JP S5573164 A JPS5573164 A JP S5573164A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- phase
- detection output
- synchronous
- giving
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/22—Demodulator circuits; Receiver circuits
- H04L27/227—Demodulator circuits; Receiver circuits using coherent demodulation
- H04L27/2271—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses only the demodulated signals
- H04L27/2273—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses only the demodulated signals associated with quadrature demodulation, e.g. Costas loop
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
PURPOSE:To realize a carrier synchronous circuit or the like with a small number and simple component parts by giving multiplication between the detection output signal and the 2-division signal of the clock and then giving the synchronous control to the phase of the reference signal with the DC component of the above multiplication and based on the minimum shift keying received input signal. CONSTITUTION:The both the sine and cosine phase comparisons are given via two phase comparators 11 and 12 between the reference carrier signal and the input signal applied to input terminal 1 to secure the in-phase and orthogonal-phase detection output. These signals are then demodulated and delivered 9 through the differential logic conversion of the detection output. Then phase comparison 16 is given to the two detection output, and the signal thus obtained is multiplied 17 by the signal obtained by giving 2-division 20 to the synchronous timing clock signal supplied to terminal 5. And the synchronous control is given to the phase of the reference signal by the DC component of the multiplication signal and based on the minimum shift keying MSK received input signal. As a result, the carrier synchronous and demodulator circuits can be realized with a small number and simple component parts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14537178A JPS5925502B2 (en) | 1978-11-27 | 1978-11-27 | MSK signal synchronous demodulation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14537178A JPS5925502B2 (en) | 1978-11-27 | 1978-11-27 | MSK signal synchronous demodulation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5573164A true JPS5573164A (en) | 1980-06-02 |
| JPS5925502B2 JPS5925502B2 (en) | 1984-06-18 |
Family
ID=15383666
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14537178A Expired JPS5925502B2 (en) | 1978-11-27 | 1978-11-27 | MSK signal synchronous demodulation method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5925502B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5922468A (en) * | 1982-07-02 | 1984-02-04 | エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン | Digital data demodulator |
| JPS59183562A (en) * | 1983-04-02 | 1984-10-18 | Nippon Hoso Kyokai <Nhk> | Code signal transmitting system |
-
1978
- 1978-11-27 JP JP14537178A patent/JPS5925502B2/en not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5922468A (en) * | 1982-07-02 | 1984-02-04 | エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン | Digital data demodulator |
| JPS59183562A (en) * | 1983-04-02 | 1984-10-18 | Nippon Hoso Kyokai <Nhk> | Code signal transmitting system |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5925502B2 (en) | 1984-06-18 |
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