JPS5584011A - Pcm-system signal recorder/reproducer - Google Patents
Pcm-system signal recorder/reproducerInfo
- Publication number
- JPS5584011A JPS5584011A JP16546978A JP16546978A JPS5584011A JP S5584011 A JPS5584011 A JP S5584011A JP 16546978 A JP16546978 A JP 16546978A JP 16546978 A JP16546978 A JP 16546978A JP S5584011 A JPS5584011 A JP S5584011A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- ffa
- counter
- field
- odd
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 abstract 6
- 230000003111 delayed effect Effects 0.000 abstract 1
Landscapes
- Synchronizing For Television (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
PURPOSE: To secure the decision for the odd and even numbers of the field by setting and resetting the FF circuit which reverses by the vertical synchronous signal in relation to the output of the counter circuit of the video synchronous signals and the delay circuit based on the vertical synchronous signals each.
CONSTITUTION: Vertical synchronous signal Sa is supplied to FFA, delay circuit B and counter C each; while video synchronous signal Sb is supplied to counter C. And FFA reverses via signal Sa. Counter C is reset by signal Sa and then carries out count-up to the prescribed number in accordance with the fall of signal Sb. In that case, signal Sd is obtained through differentiating circuit D. And if the odd field exists then, gate E is opened via the open/close control signal which is delayed more than signal Sa through delay circuit B. Thus signal SD resets FFA to secure the decision for the odd field. After this, with application of the vertical synchronous signal, FFA reverses to turn to "1" to secure the decision for the even field. In such way, the odd and even numbers can be decided for the field.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16546978A JPS5584011A (en) | 1978-12-20 | 1978-12-20 | Pcm-system signal recorder/reproducer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16546978A JPS5584011A (en) | 1978-12-20 | 1978-12-20 | Pcm-system signal recorder/reproducer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5584011A true JPS5584011A (en) | 1980-06-24 |
Family
ID=15812998
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16546978A Pending JPS5584011A (en) | 1978-12-20 | 1978-12-20 | Pcm-system signal recorder/reproducer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5584011A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57169910A (en) * | 1981-04-14 | 1982-10-19 | Akai Electric Co Ltd | Data area detecting circuit |
-
1978
- 1978-12-20 JP JP16546978A patent/JPS5584011A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57169910A (en) * | 1981-04-14 | 1982-10-19 | Akai Electric Co Ltd | Data area detecting circuit |
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