JPS5586197A - Method of fabricating multilayer circuit board - Google Patents

Method of fabricating multilayer circuit board

Info

Publication number
JPS5586197A
JPS5586197A JP16031278A JP16031278A JPS5586197A JP S5586197 A JPS5586197 A JP S5586197A JP 16031278 A JP16031278 A JP 16031278A JP 16031278 A JP16031278 A JP 16031278A JP S5586197 A JPS5586197 A JP S5586197A
Authority
JP
Japan
Prior art keywords
circuit board
multilayer circuit
fabricating multilayer
fabricating
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16031278A
Other languages
Japanese (ja)
Other versions
JPS5850437B2 (en
Inventor
Takashi Nukui
Shigeo Nakatake
Masaru Iwasaki
Katsuteru Awane
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP53160312A priority Critical patent/JPS5850437B2/en
Publication of JPS5586197A publication Critical patent/JPS5586197A/en
Publication of JPS5850437B2 publication Critical patent/JPS5850437B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Drying Of Semiconductors (AREA)
JP53160312A 1978-12-25 1978-12-25 Multilayer wiring board manufacturing method Expired JPS5850437B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53160312A JPS5850437B2 (en) 1978-12-25 1978-12-25 Multilayer wiring board manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53160312A JPS5850437B2 (en) 1978-12-25 1978-12-25 Multilayer wiring board manufacturing method

Publications (2)

Publication Number Publication Date
JPS5586197A true JPS5586197A (en) 1980-06-28
JPS5850437B2 JPS5850437B2 (en) 1983-11-10

Family

ID=15712226

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53160312A Expired JPS5850437B2 (en) 1978-12-25 1978-12-25 Multilayer wiring board manufacturing method

Country Status (1)

Country Link
JP (1) JPS5850437B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61207095A (en) * 1985-03-11 1986-09-13 イビデン株式会社 Printed wiring board for thin type id card
JPS6432698A (en) * 1987-04-13 1989-02-02 Texas Instruments Inc Plasma etching of dielectric printed wiring board blind passing-through shunt
US6326561B1 (en) 1995-07-05 2001-12-04 Hitachi, Ltd. Thin-film multilayer wiring board with wiring and via holes in a thickness of an insulating layer

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61207095A (en) * 1985-03-11 1986-09-13 イビデン株式会社 Printed wiring board for thin type id card
JPS6432698A (en) * 1987-04-13 1989-02-02 Texas Instruments Inc Plasma etching of dielectric printed wiring board blind passing-through shunt
US6326561B1 (en) 1995-07-05 2001-12-04 Hitachi, Ltd. Thin-film multilayer wiring board with wiring and via holes in a thickness of an insulating layer

Also Published As

Publication number Publication date
JPS5850437B2 (en) 1983-11-10

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