JPS56165444A - Data sampling device - Google Patents

Data sampling device

Info

Publication number
JPS56165444A
JPS56165444A JP6849980A JP6849980A JPS56165444A JP S56165444 A JPS56165444 A JP S56165444A JP 6849980 A JP6849980 A JP 6849980A JP 6849980 A JP6849980 A JP 6849980A JP S56165444 A JPS56165444 A JP S56165444A
Authority
JP
Japan
Prior art keywords
data
clock
transmitted
cycle
clock pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6849980A
Other languages
Japanese (ja)
Inventor
Yasuo Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6849980A priority Critical patent/JPS56165444A/en
Publication of JPS56165444A publication Critical patent/JPS56165444A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/20Repeater circuits; Relay circuits
    • H04L25/24Relay circuits using discharge tubes or semiconductor devices
    • H04L25/242Relay circuits using discharge tubes or semiconductor devices with retiming

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To prevent an effect of noise during a short-cycle clock, by securing a start of time limiting action by either a rise or a fall of the clock pulse with use of a delaying circuit having a delay time shorter than the data cycle. CONSTITUTION:A monostable multivibrator 1, which receives the transmitted clock pulse and is triggered by either a rise of a fall of the clock pulse, is shorter than the data cycle Td. A sampling circuit 2 receives the output of the vibrator 1 and the transmitted data and samples the data when the metastable state of the vibrator 1 ends to hold the data until the next sampling. When the clock and data are transmitted with inclusion of noise via a circuit, the output is set at a high level for the metastable time that is set previously at the final edge of the clock.
JP6849980A 1980-05-23 1980-05-23 Data sampling device Pending JPS56165444A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6849980A JPS56165444A (en) 1980-05-23 1980-05-23 Data sampling device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6849980A JPS56165444A (en) 1980-05-23 1980-05-23 Data sampling device

Publications (1)

Publication Number Publication Date
JPS56165444A true JPS56165444A (en) 1981-12-19

Family

ID=13375444

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6849980A Pending JPS56165444A (en) 1980-05-23 1980-05-23 Data sampling device

Country Status (1)

Country Link
JP (1) JPS56165444A (en)

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