JPS5715468A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the size of an FET by so removing an insulating film by a parallel planar type dry etching device as to retain the insulating film coated by a reduced pressure CVD method on the side of a gate polysilicon pattern and thus self- aligning the formation of contacts. CONSTITUTION:With an oxidized film 15 as a mask a polysilicon gate pattern 14 is sidewisely etched via a gate film 13 on a substrate 11, and a diffused layer 17 is then formed by an ion injection. Then, an Si nitrided film 18 is then accumulated by a reduced pressure CVD method, and film 18 is then etched by a parallel planar type dry etching device having a directivity, and the film 18 is retained on the side face of the polysilicon. Thereafter, an oxidized film 13 is so wet etched as to expose the layer 17, an aluminum electrode 19 is formed, and source and drain regions are connected. Thus, the contacting area with the diffused layer can be formed in the vicinity of the gate polycilicon pattern 14 without using a mask pattern, the size of the element is reduced, and the element can be integrated.