JPS57199318A - High-speed bipolar data latch circuit - Google Patents

High-speed bipolar data latch circuit

Info

Publication number
JPS57199318A
JPS57199318A JP56083788A JP8378881A JPS57199318A JP S57199318 A JPS57199318 A JP S57199318A JP 56083788 A JP56083788 A JP 56083788A JP 8378881 A JP8378881 A JP 8378881A JP S57199318 A JPS57199318 A JP S57199318A
Authority
JP
Japan
Prior art keywords
gate
circuit
gates
latch circuit
speed bipolar
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56083788A
Other languages
Japanese (ja)
Inventor
Hiroki Yamauchi
Tadanobu Nikaido
Tetsushi Sakai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP56083788A priority Critical patent/JPS57199318A/en
Publication of JPS57199318A publication Critical patent/JPS57199318A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits

Landscapes

  • Logic Circuits (AREA)

Abstract

PURPOSE:To obtain a high-speed bipolar data latching circuit less in gates for the latch circuit, with high speed and low power, by forming the circuit through the combination of three NOR gates. CONSTITUTION:A latch circuit consists of 3 NOR gates A,B and C, and data D and a clock C are inputted to the NOR gate A. An inverted clock C' and an output of the NOR gate C are inputted to the NOR gate B. Connection is made for the NOR gate C so that the output of the gates A and B is inputted. Thus, the data latch is made with the logical operation as shown in an equation. Through the formation of the circuit, a higj-speed bipolar data latching circuit with less gate numbers and low power can be obtained.
JP56083788A 1981-06-02 1981-06-02 High-speed bipolar data latch circuit Pending JPS57199318A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56083788A JPS57199318A (en) 1981-06-02 1981-06-02 High-speed bipolar data latch circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56083788A JPS57199318A (en) 1981-06-02 1981-06-02 High-speed bipolar data latch circuit

Publications (1)

Publication Number Publication Date
JPS57199318A true JPS57199318A (en) 1982-12-07

Family

ID=13812377

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56083788A Pending JPS57199318A (en) 1981-06-02 1981-06-02 High-speed bipolar data latch circuit

Country Status (1)

Country Link
JP (1) JPS57199318A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6152019A (en) * 1984-08-21 1986-03-14 Nec Corp Logic circuit
EP0524712A3 (en) * 1991-07-25 1993-06-30 Sharp Kabushiki Kaisha Logic circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6152019A (en) * 1984-08-21 1986-03-14 Nec Corp Logic circuit
EP0524712A3 (en) * 1991-07-25 1993-06-30 Sharp Kabushiki Kaisha Logic circuit
US5289518A (en) * 1991-07-25 1994-02-22 Sharp Kabushiki Kaisha Low power shift register circuit

Similar Documents

Publication Publication Date Title
JPS5373954A (en) Divider circuit
JPS57199318A (en) High-speed bipolar data latch circuit
JPS53121558A (en) Variable divider circuit
JPS5381026A (en) Latch circuit with log in-out feature
JPS546760A (en) Logic circuit
JPS5353281A (en) Semiconductor integrating circuit
JPS5367338A (en) Semiconductor logical circuit device
JPS532061A (en) Flip-flop circuit
JPS6453620A (en) Flip-flop circuit
JPS52125244A (en) Memory circuit
JPS5617516A (en) Rs flip-flop circuit
JPS5392655A (en) Logic circuit
JPS52134476A (en) Voltage inclination/time width conversion circuit
JPS5373952A (en) Flip-flop integrated circuit
JPS52116060A (en) Semiconductor unit
JPS53118988A (en) Integrated circuit device and its manufacture
JPS5754407A (en) Frequency demodulation circuit
JPS5539474A (en) Flip-flop circuit
JPS5379364A (en) Output buffer circuit
JPS5366358A (en) Logic circuit
JPS5378159A (en) Logic circuit
JPS5379339A (en) Basic circuit of progammable cmos logical array
JPS5373957A (en) Logic circuit
JPS574618A (en) Flip-flop
JPS5295938A (en) Control method of flip-flop