JPS575423A - Digital variable phase shifter - Google Patents

Digital variable phase shifter

Info

Publication number
JPS575423A
JPS575423A JP8060780A JP8060780A JPS575423A JP S575423 A JPS575423 A JP S575423A JP 8060780 A JP8060780 A JP 8060780A JP 8060780 A JP8060780 A JP 8060780A JP S575423 A JPS575423 A JP S575423A
Authority
JP
Japan
Prior art keywords
signal
terminal
counter
phase
programmable counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8060780A
Other languages
Japanese (ja)
Inventor
Eiji Itaya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8060780A priority Critical patent/JPS575423A/en
Publication of JPS575423A publication Critical patent/JPS575423A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00Networks using digital techniques
    • H03H17/08Networks for phase shifting

Landscapes

  • Filters That Use Time-Delay Elements (AREA)

Abstract

PURPOSE:To accomplish an arbitrary amount of phase shift in an arbitrary step by digital control, by using a phase locked loop (PLL) and a counter. CONSTITUTION:A signal applied to an input terminal 1 is respectively given to a PLL circuit 2, phase comparator 3, set terminal S of an FF7 and load terminal L of a programmable counter 8, and a signal multiplying the input signal by N, where the frequency dividing ratio of a frequency divider 6 is N, is applied as a clock to a clock terminal CLK of the programmable counter 8 from a VCO 5. Further, an output at a termnal Q of the FF7 is applied to an enable terminal E of the programmable counter 8 and the output signal is applied to a reset terminal R of the FF7. When a control signal S1 sets the frequency dividing ratio of the frequency divider 6 as N and a control signal S2 sets the number of counts of te counter 8 as M, the signal phase is (360XM/N).
JP8060780A 1980-06-14 1980-06-14 Digital variable phase shifter Pending JPS575423A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8060780A JPS575423A (en) 1980-06-14 1980-06-14 Digital variable phase shifter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8060780A JPS575423A (en) 1980-06-14 1980-06-14 Digital variable phase shifter

Publications (1)

Publication Number Publication Date
JPS575423A true JPS575423A (en) 1982-01-12

Family

ID=13723010

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8060780A Pending JPS575423A (en) 1980-06-14 1980-06-14 Digital variable phase shifter

Country Status (1)

Country Link
JP (1) JPS575423A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0780975A1 (en) * 1995-12-21 1997-06-25 HE HOLDINGS, INC. dba HUGHES ELECTRONICS Precision digital phase shifter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0780975A1 (en) * 1995-12-21 1997-06-25 HE HOLDINGS, INC. dba HUGHES ELECTRONICS Precision digital phase shifter

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