JPS5787176A - Fabrication of semiconductor device - Google Patents

Fabrication of semiconductor device

Info

Publication number
JPS5787176A
JPS5787176A JP55163556A JP16355680A JPS5787176A JP S5787176 A JPS5787176 A JP S5787176A JP 55163556 A JP55163556 A JP 55163556A JP 16355680 A JP16355680 A JP 16355680A JP S5787176 A JPS5787176 A JP S5787176A
Authority
JP
Japan
Prior art keywords
gate
control gate
polycrystalline silicon
layers
floating gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55163556A
Other languages
Japanese (ja)
Inventor
Masahiro Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP55163556A priority Critical patent/JPS5787176A/en
Publication of JPS5787176A publication Critical patent/JPS5787176A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/68Floating-gate IGFETs
    • H10D30/681Floating-gate IGFETs having only two programming levels
    • H10D30/684Floating-gate IGFETs having only two programming levels programmed by hot carrier injection
    • H10D30/686Floating-gate IGFETs having only two programming levels programmed by hot carrier injection using hot carriers produced by avalanche breakdown of PN junctions, e.g. floating gate avalanche injection MOS [FAMOS]

Landscapes

  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To obtain an FAMOS transistor free from disconnection in a silicon gate MOS transistor with two gate layers consisting of a floating gate and control gate layers by diffusing impurities into both the layers of polycrystalline silicon. CONSTITUTION:Thick field oxide film 204 is formed on the periphery of a silicon substrate 201 so as to surround its internal regions. On the internal surface of the substrate 201, a thin gate oxide film 202 is formed and on which the floating gate 203 of polycrystalline silicon is formed at its center. Then, the control gate 206 of polycrystalline silicon is provided on the floating gate with a gate oxide coating 205 interlaid for formation of an FAMOS transistor. In such structure, normally diffusion of impurities is introduced only into the floating gate 203, not into the control gate 206. This particular type of semiconductor, however, provides the control gate 206 also with approximately the same degree of diffusion, so that there is no fear of disconnection of aluminum wiring on the control gate.
JP55163556A 1980-11-20 1980-11-20 Fabrication of semiconductor device Pending JPS5787176A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55163556A JPS5787176A (en) 1980-11-20 1980-11-20 Fabrication of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55163556A JPS5787176A (en) 1980-11-20 1980-11-20 Fabrication of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5787176A true JPS5787176A (en) 1982-05-31

Family

ID=15776137

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55163556A Pending JPS5787176A (en) 1980-11-20 1980-11-20 Fabrication of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5787176A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5147813A (en) * 1990-08-15 1992-09-15 Intel Corporation Erase performance improvement via dual floating gate processing
US5229631A (en) * 1990-08-15 1993-07-20 Intel Corporation Erase performance improvement via dual floating gate processing

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5259585A (en) * 1975-10-29 1977-05-17 Intel Corp Method of producing mos polycrystalline ic
JPS5488087A (en) * 1977-12-23 1979-07-12 Ibm Method of fabricating fet

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5259585A (en) * 1975-10-29 1977-05-17 Intel Corp Method of producing mos polycrystalline ic
JPS5488087A (en) * 1977-12-23 1979-07-12 Ibm Method of fabricating fet

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5147813A (en) * 1990-08-15 1992-09-15 Intel Corporation Erase performance improvement via dual floating gate processing
US5229631A (en) * 1990-08-15 1993-07-20 Intel Corporation Erase performance improvement via dual floating gate processing

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