JPS58170832U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS58170832U
JPS58170832U JP1982068422U JP6842282U JPS58170832U JP S58170832 U JPS58170832 U JP S58170832U JP 1982068422 U JP1982068422 U JP 1982068422U JP 6842282 U JP6842282 U JP 6842282U JP S58170832 U JPS58170832 U JP S58170832U
Authority
JP
Japan
Prior art keywords
semiconductor equipment
semiconductor chip
metal substrate
plastic
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1982068422U
Other languages
English (en)
Inventor
山岸　始男
伸一 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP1982068422U priority Critical patent/JPS58170832U/ja
Publication of JPS58170832U publication Critical patent/JPS58170832U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07353—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/331—Shapes of die-attach connectors
    • H10W72/334—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は本考案の対象の一例のモールド形半導体装置の
斜視図、第２図はそのリードフレームの支持体部の従来
例の平面図、第３図は同じく側面図、第４図は本考案の
一実施例によるリードフレーム支持体部の平面図、第５
図はその一部拡大図、第６図は同じく側面図である。 １・・・リードフレーム支持体、１１・・・支持面、３
・・・プラスチック、４・・・半導体チップ、５・・・
細溝。

Claims (1)

    【実用新案登録請求の範囲】
  1. 金属基板上に半導体チップを装着し、プラスチックモー
    ルドしてなるものにおいて、金属基板の半導体チップ支
    持面に縦横に走る細溝が設けられたことを特徴とする半
    導体装置。
JP1982068422U 1982-05-11 1982-05-11 半導体装置 Pending JPS58170832U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1982068422U JPS58170832U (ja) 1982-05-11 1982-05-11 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1982068422U JPS58170832U (ja) 1982-05-11 1982-05-11 半導体装置

Publications (1)

Publication Number Publication Date
JPS58170832U true JPS58170832U (ja) 1983-11-15

Family

ID=30078205

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1982068422U Pending JPS58170832U (ja) 1982-05-11 1982-05-11 半導体装置

Country Status (1)

Country Link
JP (1) JPS58170832U (ja)

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