JPS58212324A - Method of controlling power source - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power supply control method that can be used to control one source of a television receiver, and is a control method having a time measurement function (hereinafter referred to as a timer). In a circuit, when trying to reset a switching circuit based on the result of time measurement, whether the switching circuit is a normal on/off element or a self-protecting type switching element,
When the power to the controlled circuit connected to the control circuit and the switching circuit is cut off during time measurement, if the power is immediately restored by a momentary cutoff that does not disturb the operation of the circuit, the state of the switching circuit remains the same. Therefore, in the event of a relatively long power outage that would cause the timer to continue operating and disrupt the operation of the circuit, it is possible to protect the controlled circuit by resetting the state of the switching circuit and canceling the timer. The aim is to provide a power supply control method that can

Conventionally, the circuit shown in FIG. 1 is often used.

In FIG. 1, 1-1 is a timer control circuit, 1-2 is a timer circuit, 1-3 is a switching circuit, 1-4 is a controlled circuit, 1-6 is a power supply circuit, and 1-6 is a power supply.

In such a structure, in order not to affect the controlled circuit 1-4 even if the power is cut off momentarily, the time constant of the power supply circuit 1-5 is increased and the time constant of the power supply circuit 1-5 is increased. I am trying to retain the output.

Power supply 1 during the period when power supply circuit 1-6 can maintain normal voltage
-6, the timer circuit 1-2 maintains the state before being shut off, and when the power supply 1-6 is shut off during a period in which no further power supply circuits can maintain normal voltage, The timer circuit 1-2 cancels the period measurement function.

Here, when a self-holding type switching element is used in the switching circuit 1-3, in the conventional method, when the switching circuit 1-3 is set and measuring time, it is possible to prevent the power from being cut off for a relatively long period of time. Then, when the power is restored next time, the timer function is canceled from the above example, but the switching circuit 1-3 is designed to be reset.

This is one method, but even though the user has set the timer so that the switching circuits 1-3 will be reset after a certain period of time, the timer may be reset due to a relatively long power interruption while the timer is being set. The setting is canceled, the switching circuit 1-3 remains set, and the next time the power is restored, power is applied to the controlled circuit.

7-゛If we take the example of a television set, the user sets a timer and the power goes out while he is watching TV, and he goes out. When the power is restored and the power is turned back on, the television set remains on, causing the television set to overheat and become dangerous.

The present invention eliminates the above unreasonableness by using a non-volatile memory element and detecting the power state, and when the timer is set while the switching circuit is set, the timer setting state is changed. It is stored in non-volatile memory, and when the power is turned off for a relatively long period of time, the previous timer setting state is continued from the non-volatile memory, and if the timer was set in the previous state, This is a power supply control method that protects the controlled circuit by resetting the switching circuit and preventing the application of power supply voltage to the controlled circuit.Examples of the present invention will be described below with reference to the drawings.

Figure 2? d1 This shows an apparatus in which the power supply control method of the present invention is implemented, and in FIG. 2, 2-1 is a remote control signal receiving section, 2-2 is a key operation section, 2-3 is a control circuit, 2-4 is a non-volatile memory, 2-6 is a power supply circuit, 2-6
2 is a reset circuit, 2-7 is a switching circuit, 2-8 is a timer display circuit, and 2-9 is a controlled circuit.

Various controls are performed by a control circuit 2-3 by inputting a remote control signal A and a key operation section 2-2. The control circuit 2-3 has a time measurement function and drives a display circuit 2-8 that displays the state, a nonvolatile memory 2-4 that stores the state, and a switching circuit 2-7. Also,
Power for the control circuit 2-3 is supplied from a power supply circuit 2-6, and the reset circuit 2-6 detects the state of the power supply, and has the function of setting the control circuit to an initial state or operating it. Further, 2-7 is a switching circuit which may be any switching element, and is driven by a control circuit signal F to switch the power supply of the controlled circuit 2-9.

To simplify the explanation, the operation of the control circuit 2-3 will be limited to driving the nonvolatile memory 2-4, the display circuit 2-8, and the switching circuit 2-7. switching circuit 2
The set state of -7 means that power is applied to the controlled circuit 2-9, and the reset state means that the power is cut off.

First, the reset circuit 2-6 will be explained. As shown in FIG. 3a, when the power supply voltage C is applied to the reset circuit (point A), the output of the power supply circuit 2-6 is as follows.
As shown in FIG. 3C, the reset signal E increases at a point 2 where it exceeds a certain set voltage H, and becomes a low level and a high level at a point 3, as shown in FIG. 3C. At this time, it is assumed that the control circuit 2-3 is in an initial state when the signal Σ is at a low level, and starts operating when the signal Σ is at a high level. Here, if the threshold value H of the reset signal is set appropriately by providing a time constant to the power supply circuit 2-6, the voltage is DI,i can be set as shown in FIG. 3, and the reset signal remains at a high level.

However, when the power is interrupted for a relatively long time, such as in section C in Figure 3a, the voltage -i becomes as shown in Figure 3A, and becomes less than the reset threshold value H. From there, the reset signal E becomes low level as shown in FIG. 3C.

Next, an example of a driving method for the nonvolatile memory 2-4 will be explained. The nonvolatile memory 2-4 normally rewrites and retains data in the memory through data writing and erasing operations.
It stores its contents for a certain period of time even when the power is turned off. In many cases, a memory element has an address, and data can be sequentially output, written, and erased with respect to the designated address. Each operation is performed using the signal B in Figure 2.
The signal format differs depending on the memory. Currently, the typical types of control are (1) address input, (II) data succession, and (iii)
) data erase, Gv) data input, and (V) data write operations. Each operation will be explained with reference to FIG. In FIG. 4, 4-1 is an address register that specifies a memory address. 4-2 is a 11-' nonvolatile memory element, 4-3 is a data register used for data transfer, 4-4 is a control circuit for performing each operation, and 4-6 is for data/address input. Data lines 4-6 indicate the memory control clock.

In the operation (1) above, address data is sent to the address register 4-1 via the control register 4-4 in response to the signal B, and a certain address within the memory element 4-2 is designated.

The operation (11) above reads the memory contents at the address specified in (1) to the data register 4-3 and outputs it to the signal B. The data read at this time may be taken out as a signal separate from signal B in (1).

(iii) n If the data input to the control register 4-4 is an erase command, the memory contents at the address specified in (1) are erased.

The above (IV) is 6 to 1 data register 4 by signal B.
-3 Enter the data.

(■) Vi above, if the data input to the control register 4-4 is a write command, the data register 4-3 is stored in the memory at the address specified in (1) and JP-A-58-212324 (4). Write the contents.

Based on the above operation, the operation of the control circuit 2-3 of the present invention will be explained with reference to the flowcharts of FIGS. 6, 6, and 7.

First, one address, for example, "T" in the nonvolatile memory 2-4 of FIG. 2 is used as a memory in a timer setting state. Now, when the timer state is released and the switching circuit state (hereinafter abbreviated as switch state) is in the reset state, when the power supply C is turned on, the control circuit operates from the initial state by the signal E of the reset circuit 2-(5). The first step is to set the initial value, and the second step is to read the timer state data from the memory address (l T II).The third step is to determine the timer state. Since it is assumed that this is cancelled, we move on to step 6.

Now, since we are talking about timer setting and removal, step 7 is in progress, but step 8 is the one that extracts the timer setting/cancellation process 3. This is the ninth process, and the tenth process is the process of setting and resetting the switching circuit. This is the eleventh process. Now, when the control signal is not input, the control circuit operates in the 8th. 9th, 10th. The process of moving from the 11th process and returning to the 6th process is repeated.

Here, when a control signal to set the switching circuit 2-7 is input, the process is determined in step 10 in FIG. 5, moves to step 4, and sends a signal to set the switch to path F. Output.

Considering that in this state, the power supply C is cut off, the reset circuit 2-6 operates, and the control circuit 2-3 returns to the initial state, the timer state is released, so the first. Second. The process passes through the third process and moves on to the sixth process.

At this time, if the switch element is a self-holding type, the switch state is in a set state.

Then, since the timer state has been canceled, the 5th and 7th stages.
8th. 9th. 10th. It passes through the 11th process and returns to the 6th process. Therefore, in the timer release state, the state of the switching circuit 2-7 is maintained as it is by turning on and off the power supply C.

Now, if a timer setting signal is input, it is determined in step 8, and the process moves to step 13 shown in FIG. 6, where the timer counter setting for time measurement is performed and the timer display circuit 2-8 is set. turns on and stores address data in memory 2-4.
", then input "timer setting data", erase address "T"' of memory 2-4, and write "timer setting data"' to memory 2-4. Then,
Since the timer is in the setting state, the process moves to step 6, where the timer count function is performed until the timer reaches a predetermined value, that is, until the timer counter does not overflow, it moves to step 7, and step 8. 9th. No. 10.

Proceed to step 11 and step 6. The processing returns to the sixth step. In this state, when the timer counter overflows,
It is determined in the sixth step, the process proceeds to the twelfth step, the timer counter setting is canceled, the timer display circuit 2-8 is turned off,
Input memory 2-4 K address data “T”,
Furthermore, input the patimer release data'' and
After erasing the address "T" and writing the patimer release data into the memory 2-4, the switch set state is output from the F path, and the switching circuit is reset.

Now, in the switch set state and timer setting state, if the power supply C is cut off for a period during which the reset circuit 2-6 does not go to low level, the control circuit 2-3 continues to operate without returning to the initial state. . However, when the power supply C is cut off for a period during which the reset circuit 2-6 becomes low level, the control circuit returns to its initial state.

At this time, the initial value is set in the first step, the timer status is read from the memory in the second step, and the state is determined to be "PA setting" in the third step, and the process moves to step 12 in FIG. Cancel timer settings and turn off timer display.

Write the "timer release data" to address "T" in the memory and reset the switching circuit. , , , , 1 Therefore, when the power supply C is restored to the timer circuit in the switch sent state, The switching circuit 2-71rl enters the reset state, and the controlled circuit is protected without being supplied with power.

Also, in the timer setting state, when a timer release signal is input, it is determined in step 9, and the process moves to step 14 in FIG. 7, where the timer counter setting is canceled, the timer display is turned off, and the address data is stored in the memory. After inputting ``T'', further inputting ``timer release data'', erasing Atrea ゛T'' in the memory, and writing the ``timer release data'' into the memory, the process returns to the fifth step and subsequent steps.

As described above, according to the present invention, when a timer is set in a state where a switching circuit that turns on and off the power of a controlled circuit is set, the timer setting state is stored in a nonvolatile memory, and the power supply is maintained for a relatively long period. When the power is turned off, the timer setting state is read from the non-volatile memory and the switching circuit is reset, so the power will not remain on.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a power supply control device in a conventional example.
FIG. 2 is a block diagram of a power supply control device implementing the power supply control method of the present invention, and FIGS. 3a and 3b. C is a characteristic diagram for explaining the device, FIG. 4 is a specific block diagram of a part of the device, and FIGS. 6, 6, and 7 are flowcharts for explaining the device. -3... Control circuit, 2-7... Switching circuit, 2-9... Controlled circuit, 2-6
...Reset circuit, 2-6...Power supply circuit, 2-4...Nonvolatile memory. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3 Figure 11 I4 Figure i5

Claims (1)

[Claims] (1) When the time measurement function is set with a switching circuit that controls turning off and on of power to the controlled circuit set, storing this time setting state in a nonvolatile memory; 1. When the power is turned off for a certain period of time and the power is turned off again. :imm
If the switching circuit state is held in the set state and the power is cut off for a certain period of time, when the power cut off state is restored, the above time setting state is read out from the nonvolatile memory and read out. A method of power supply control characterized by placing the switching circuit in a reset state using a signal. (2) When the operation starts from the initial state, one address of the nonvolatile memory is used as a timer state memory, and the first step is to set the initial value, and the second step is to read the timer state data from the timer state memory. '・-゛2 process, a 3rd process to determine whether the read timer state data in 3 is a set state or a released state, and a 46 process to determine whether it is a timer set state when it is in a "released state". and,
a seventh disaster stage for performing processing other than setting and canceling the timer and setting and resetting the switching circuit when in the release state;
an eighth step of determining whether to set the timer; a ninth step of determining whether to cancel the timer; and a tenth step of determining whether to set the switching circuit;
an eleventh step of determining whether to reset the switching circuit; and an eighth step. 9th. 10th. 2. The power supply control method according to claim 1, wherein if no processing is performed as a result of the determination in the eleventh step, the process returns to the sixth step. (3) When the timer role signal is determined in the eighth step, the timer counter is set, the timer is displayed as on, and the timer setting data is written in the timer state memory. , when the timer release signal is determined, the timer counter setting is canceled, the timer display is turned off, and the timer release data is written in the timer status memo 3.
In the 0th process, when the switching circuit set signal is determined, the control process passes through the 4th process of outputting the set signal to the switching circuit and proceeds to the 5th process, and in the 11th process, the switching circuit reset signal is determined. When the timer counter is reset, a timer off display is displayed, timer release data is written in the timer state memory, and a signal for resetting the switching circuit is output. A power supply control method according to claim 2. (4) When in the timer setting state, the timer setting state is determined in the sixth step, the timer is counted in the sixth step, and until the timer count ends, the 7th. 8th. 9th. 10th. 11th process, 6th process, and in the 6th process, when the rippa and toyma count are completed, the process moves to the 12th process, the timer counter setting is canceled, and the timer off display is performed.
After writing the timer release data to the timer state memory and outputting a signal to reset the switching circuit, the sixth
The power supply control method according to claim s2, characterized in that the method moves to a step. (6) When the control circuit returns to the initial state in the timer setting state, the first step is to set the initial value, the second step is to read the timer state from the timer state memory, and the timer state data is When it is in the setting state, it is determined in the third step, and the process moves to the twelfth step, where the timer counter setting is canceled, a timer off display is made, timer cancellation data is written in the timer state memory, and a signal for resetting the switching circuit is output. A power supply control method according to claim 2, characterized in that: