JPS585122U - key identification circuit - Google Patents
key identification circuitInfo
- Publication number
- JPS585122U JPS585122U JP7454982U JP7454982U JPS585122U JP S585122 U JPS585122 U JP S585122U JP 7454982 U JP7454982 U JP 7454982U JP 7454982 U JP7454982 U JP 7454982U JP S585122 U JPS585122 U JP S585122U
- Authority
- JP
- Japan
- Prior art keywords
- key
- terminal
- identification signal
- key identification
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Input From Keyboards Or The Like (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のキー識別回路の結線図、第２図は他の従
来のキ」識別回路を示す結線図、第３図は本考案のキー
識別回路の一実施例を示す結線図である。
５０、 ５１． ５２・・・・・・第１のキー識別信号
入力端子、５３．５４．５５． ７４．８２・・・・・
・ＯＲゲート、５６・・・・・・ＲＳフリップフロップ
、５７゜５８・・・・・・第２のキー識別信号入力端子
、５９゜６０．６１・・・・・・キー人力信号線路、６
２． ６３゜６４・・・・・・キー出力信号線路、６５
〜７３・・・・・・キースイッチ、７５・・・・・・第
１のキー識別信号出力端子、７６．７７．７８・・・・
・−ＡＮＤゲート、？９，８０゜８１・・・・・・第３
のキー識別信号入力端子、８３・・間第２のキー識別信
号出力端子、８４・・・・・・第２のＲＳフリップフロ
ップ、８５・・・・・・第４のキー識別信号入力端子。Fig. 1 is a wiring diagram of a conventional key identification circuit, Fig. 2 is a wiring diagram showing another conventional key identification circuit, and Fig. 3 is a wiring diagram showing an embodiment of the key identification circuit of the present invention. . 50, 51. 52...First key identification signal input terminal, 53.54.55. 74.82...
・OR gate, 56... RS flip-flop, 57° 58... Second key identification signal input terminal, 59° 60.61... Key human power signal line, 6
2. 63゜64...Key output signal line, 65
~73... Key switch, 75... First key identification signal output terminal, 76.77.78...
・-AND gate? 9,80°81...3rd
key identification signal input terminal, 83... second key identification signal output terminal, 84... second RS flip-flop, 85... fourth key identification signal input terminal.
Claims (1)
トリクス状に交差せしめ、その各交差点にそれぞれ接続
された複数のキースイッチと、上記複数のキー人力信号
線路にそれぞれ出力端子が接続され、一方の入力端子に
それぞれ複数の第１のキー識別信号入力端子が接続され
た複数の第１のＯＲゲートと、上記複数の第１のＯＲゲ
ートの他方の入力端子に出力端子が接続され、リセット
端子及びセット端子にそれぞれ複数の第２のキー識別信
号入力端子が接続された第１のＲＳフリップフロップと
、上記複数のキー出力信号線路に゛それぞれ入力端子が
接続され、出力端子に第１のキー識別信号出力端子が接
続された第２のＯＲゲートと、上記複数のキー出力信号
線路にそれぞれ一方の入力端子が接続され、他方の入力
端子にそれぞれ複数の第３のキー識別信号入力端子が接
続された複数のＡＮＤゲートと、上記複数のＡＮＤゲー
トのそれぞれの出力端子がそれぞれ入力端子に接続され
、出力端子が第２のキー識別信号出力端子に接続された
第３のＯＲゲートとを備え、上記第１のＲＳフリップフ
ロップによる複数の第１のＯＲゲートへの一斉出力によ
って上記第３のＯＲゲートに出力が発生したことにより
キースイッチのいずれかが導通状態であることを検出し
、第１、第２のキー識別信号入力端子を順次駆動して導
通状態にあるキースイッチを識別するように構成し、複
数の第１のＯＲゲートの一方の入力端子に複数の第１の
キー識別信号入力端子がそれぞれ接続される接続線路の
１部もしくは全部に第２のＲＳフリップフロップを設け
、該第２のＲＳフリップフロップの出力端子を上記第１
のＯＲゲートの一方の入力端子に接続すると共にそのセ
ット端子を上記第１のキー識別信号入力端子に接続し、
かつ上記第２のＲＳフリップフロップのリセット端子を
第４のキー識別信号入力端子に接続したことを特徴とす
るキー識別回路。A plurality of key human power signal lines and a plurality of key output signal lines intersect in a matrix, a plurality of key switches are respectively connected to each intersection, and an output terminal is connected to each of the plurality of key human power signal lines; a plurality of first OR gates each having a plurality of first key identification signal input terminals connected to its input terminal, an output terminal being connected to the other input terminal of the plurality of first OR gates, and a reset terminal; and a first RS flip-flop whose set terminals are connected to a plurality of second key identification signal input terminals, whose input terminals are respectively connected to the plurality of key output signal lines, and whose output terminals are connected to a first key identification signal input terminal. One input terminal is connected to each of the second OR gate to which the identification signal output terminal is connected and the plurality of key output signal lines, and each of the plurality of third key identification signal input terminals is connected to the other input terminal. a plurality of AND gates, each output terminal of each of the plurality of AND gates is connected to an input terminal, and an output terminal is connected to a second key identification signal output terminal, When the first RS flip-flop generates an output to the third OR gate, it is detected that one of the key switches is in a conductive state, and the first , the second key identification signal input terminals are sequentially driven to identify a key switch in a conductive state, and the plurality of first key identification signal input terminals are input to one input terminal of the plurality of first OR gates. A second RS flip-flop is provided in part or all of the connection lines to which the terminals are respectively connected, and the output terminal of the second RS flip-flop is connected to the first
and connect the set terminal to one input terminal of the OR gate, and connect the set terminal to the first key identification signal input terminal,
A key identification circuit characterized in that the reset terminal of the second RS flip-flop is connected to a fourth key identification signal input terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7454982U JPS5819621Y2 (en) | 1982-05-20 | 1982-05-20 | key identification circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7454982U JPS5819621Y2 (en) | 1982-05-20 | 1982-05-20 | key identification circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS585122U true JPS585122U (en) | 1983-01-13 |
| JPS5819621Y2 JPS5819621Y2 (en) | 1983-04-22 |
Family
ID=29870322
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7454982U Expired JPS5819621Y2 (en) | 1982-05-20 | 1982-05-20 | key identification circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5819621Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60177313U (en) * | 1984-05-02 | 1985-11-25 | 長谷川 武夫 | Special nails for foam concrete |
-
1982
- 1982-05-20 JP JP7454982U patent/JPS5819621Y2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60177313U (en) * | 1984-05-02 | 1985-11-25 | 長谷川 武夫 | Special nails for foam concrete |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5819621Y2 (en) | 1983-04-22 |
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