JPS5851468B2 - vertical deflection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a vertical deflection circuit that can be used in a television receiver.

A conventionally used vertical deflection circuit is shown in Fig. 1.
The waveforms at each point in the figure are shown in FIG.

In FIG. 1, 1 is a switching transistor, the vertical oscillation output pulse shown in FIG. From the charging/discharging circuit lζ, a sawtooth voltage waveform shown in FIG. 2 appears at point b.

By changing the resistance value of the variable resistor 2, the amplitude of the sawtooth wave is changed to set the vertical amplitude of the screen.

Block 4 is a linearity adjustment circuit that adjusts the vertical linearity of the screen by a signal appearing at negative feedback resistor 5.

6 is a drive stage input coupling capacitor and a capacitor for smoothing the negative feedback pulse signal supplied from the output stage midpoint voltage stabilizing transistor 7;
By changing the DC potential across the drive transistor 8
The voltage at the midpoint (point d) of the output stage is stabilized by controlling the base voltage of the output stage.

A voltage waveform as shown in FIG. 2c is applied to the base of the drive transistor 8.

9 is an emitter resistance, 10 is a collector resistance, and 11.12 is a diode that compensates for the base-emitter threshold voltage of the output transistor 13.14.

At point d, which is the midpoint of the output stage, an output waveform as shown by the solid line in FIG. 2d appears.

15 is for improving the efficiency of the vertical deflection circuit by switching the power supply voltage of the drive stage and output stage to the circuit power supply voltage vB during the scanning period, and to 2VB, which is twice the circuit power supply voltage, only during the retrace time. It is a switch circuit.

As a result, the output has a voltage waveform as shown in FIG. 2d.

16 is an output coupling capacitor, and 17 is a vertical deflection coil.

As mentioned above, the transistor 7 is an output stage midpoint voltage stabilizing transistor, the base voltage of which is determined by the resistors 18 and 19, and operates only during the retrace period.

Resistors 20, 21. The capacitor 22 constitutes a filter circuit, and the average voltage Vo of the voltage waveform at point d appears at point f, as shown by the chain line in FIG. 2d.

At the emitter point e of the transistor 7, as shown in Figure 2 e, the voltage waveform at point f and the voltage waveform at point d are connected to a resistor 20°21.
A voltage waveform divided by .

The operation of transistor 7 will be briefly explained.

When the DC level of the output stage midpoint voltage changes, the DC potential VO at point f, which is its average value, changes accordingly.

The peak value of the retrace pulse of the waveform at point d is 2VB and constant, as shown in Fig. 2 d, so the peak value of the waveform ■ep shown in Fig. 2 e changes according to changes in VO. .

Transistor 7 operates in response to this change in V and applies a control signal to the base circuit of transistor 8.

This control signal is a pulse signal only during the retrace period, and is converted into a DC signal by the circuit of the coupling capacitor 6 and the resistor 23 connected to the input circuit of the drive stage as described above. The capacitor 6 is charged with the output signal and discharged during the scanning period, but if the discharge time constant is made sufficiently larger than the scanning period, it is converted to a DC signal) Average voltage value at point d.

The base bias of transistor 8 is controlled so that .

As can be seen from the circuit of FIG. 1, it is inconvenient that there are too many terminals to make this circuit into an integrated circuit as it is, and it is necessary to reduce the number of terminals as much as possible.

A circuit according to the invention, which is a circuit configuration suitable for an integrated circuit, is shown in FIG.

The same parts as in FIG. 1 will be described with the same numbers.

The difference from the circuit shown in FIG. 1 is that the drive stage and the sawtooth wave generating circuit are directly connected, and a resistor 24 and an emitter follower transistor 25 are connected to the emitter of the switching transistor 1.

How the output stage midpoint voltage is stabilized by the circuit of FIG. 3 will be explained using the waveform diagram of FIG. 4.

At point e, as shown in Fig. 4e, the average level Vo of the midpoint voltage of the output stage is the peak value ■.

, appears and is applied to the emitter of the transistor 7, which functions as a voltage comparison circuit.

Transistor 7 is turned on at the pulse portion of the waveform at point e,
As shown in FIG. 4q, a pulse waveform with a peak value of ■ appears at the nine collector output points of this transistor 7, and this V
l, (7) value changes depending on the value of Vo.

That is, as Vo increases, ■ also increases.

This pulse waveform at point q is supplied to the emitter of the switching transistor 1 through the emitter follower transistor 25.

Therefore, the pulse current ip supplied from the transistor 25 and the discharge current id that discharges the charge stored in the capacitor 3 through the transistor 1 flow through the resistor 24, and the emitter of the transistor 1 is shown by the dotted line in FIG. A pulse signal whose peak value is VRI appears.

The difference between VR24P and VR24L is the discharge current 1d (end) (ip) after the capacitor 3 starts discharging and when it ends.
This is due to the difference in the value of R24L-R2゜(ip+1d(end)):
It can be approximated by V - VBE (VBE: ) base-emitter forward voltage of transistor 25).

Next, regarding the sawtooth wave appearing at six points on the collector of transistor 1, this waveform is shown by the solid line in FIG.

The DC level of this waveform is determined by the DC level ■bL at the end of discharge of the charge in the capacitor 3.

This is because a charging current flows from the power supply vB to the capacitor 3 through the variable resistor 2 with this VbL as a reference, creating a sawtooth wave.

And VbL is determined by the following formula.

VbL; V□B(sat)+VB2+L'; Vc
B (sat) + V - VBB (however, VcB (sat
) is the collector-emitter saturation voltage of transistor 1) VcB(sat) and VBB are constant once the element is determined, so VbL is 9. will be controlled by.

Now, if the average value Vo of the output stage midpoint voltage increases, ■ also increases, and as a result, vbL also increases,
The DC level of the sawtooth wave voltage at point b increases, and by biasing the drive transistor 8 in the ON direction, the voltage level at the midpoint of the output stage is lowered, and an equilibrium state is maintained at a certain constant value. becomes stable.

By applying the pulse signal during the retrace period as a negative feedback signal to the emitter of the switching transistor 1, the coupling capacitor is omitted and the drive stage and the sawtooth wave generation circuit are directly connected, making it suitable for an integrated circuit (with a small number of terminals). The output stage midpoint voltage can be stabilized by using a circuit configuration that reduces the

FIG. 5 shows another embodiment of the invention.

The difference from FIG. 3 is that a signal obtained by superimposing a vertical oscillation pulse on a DC signal obtained by smoothing the output voltage waveform is used as the negative feedback signal.

To explain the operation of this circuit, the resistor 26 and capacitor 2
The output voltage waveform is smoothed by the smoothing circuit No. 7, and a DC signal with the average value Vo of the output stage midpoint voltage is obtained at point f (Fig. 6 f).
waveform diagram).

On the other hand, due to the circuit of transistors 28 and 29, the peak value of the collector of transistor 28 has a value of approximately ■R,
A pulse signal appears having the same pulse width as the vertical oscillation pulse.

This pulse signal is synthesized in a circuit of resistors 31 and 32 based on a DC signal having an average level of the output stage midpoint voltage appearing at the emitter of the transistor 30, and a waveform as shown in Fig. 6 e appears at point e. .

The peak value ■ep of the pulse of this waveform is expressed by the following formula.

Ivy forward voltage.

As can be seen from the above formula, ■BvBE is constant, so
■6. changes depending on the value of Vo.

By applying this signal to the emitter of the transistor 7, the output stage midpoint voltage can be stabilized as in FIG. 3, and the same effect as the circuit in FIG. 3 can be obtained.

Although the above description has been made as an output stage midpoint voltage stabilizing circuit of the B-class OTL system, it is clear that it can be used as a bias stabilizing circuit of the A-class output stage.

As described above, according to the present invention, by adding the pulse signal during the retrace period as a negative feedback signal to the emitter circuit of the switching transistor that constitutes the sawtooth voltage generation circuit, a coupling capacitor that is too large to be incorporated into an integrated circuit can be used. The midpoint voltage of the output stage can be stabilized using a circuit suitable for integrated circuits, in which the drive stage and the sawtooth wave generating circuit are directly connected to reduce the number of terminals.

Note that a vertical oscillation pulse signal may be used as the pulse signal.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of a conventional vertical deflection circuit, Figure 2 a, b,
c, d, and e are waveform diagrams of various parts of the circuit in Fig. 1, Fig. 3 is a circuit diagram of a vertical deflection circuit in an embodiment of the present invention, and Fig. 4 e.
, q and b are waveform diagrams of various parts of the circuit of FIG. 3, FIG. 5 is a circuit diagram of a vertical deflection circuit in the same embodiment, and FIGS. 6f and e are waveform diagrams of various parts of the circuit of FIG. 1.7.8...Transistor, 17...
・Vertical deflection coil, 20, 21...Resistance.

Claims (1)

[Scope of Claims] 1. A DC-coupled sawtooth wave voltage generation circuit, a vertical drive stage, a vertical output stage, and a voltage comparison circuit having two input terminals, wherein one input terminal of the voltage comparison circuit has A reference voltage is applied, a pulse whose peak value changes according to a change in the average voltage value of the output signal of the vertical output stage is applied to the other input terminal, and the output of this voltage comparison circuit is converted into the sawtooth wave voltage. A vertical deflection circuit characterized by stabilizing bias by controlling the DC level of a sawtooth voltage waveform applied to a generating circuit. 2 As a sawtooth wave voltage generation circuit, a circuit including a switching transistor and a capacitor for generating sawtooth wave voltage, and a second transistor emitter-coupled with the switching transistor is used, and a voltage is applied to the base of the second transistor. 2. The vertical deflection circuit according to claim 1, wherein the output of the comparison circuit is applied to the vertical deflection circuit. 3. A smoothing circuit for extracting the average voltage value of the output signal of the vertical output stage as means for applying a pulse whose peak value changes according to the average value of the output signal of the vertical output stage to the other input terminal of the voltage comparison circuit. , a switch circuit that responds to the output from the vertical oscillation circuit and an adder is used, the output of the smoothing circuit and the output of the switch circuit are applied to the adder, and the output of the adder is compared with the voltage. 3. The vertical deflection circuit according to claim 1, wherein the voltage is applied to the other input terminal of the circuit. 4. The voltage comparator circuit applies a pulse directly extracted from the vertical retrace pulse signal to one input terminal so that the peak value changes according to changes in the average voltage value of the output signal of the vertical output stage. 3. A vertical deflection circuit according to claim 1 or 2, characterized in that the vertical deflection circuit comprises: