JPS5866162A - Program evaluating and testing device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a general-purpose program evaluation test device for testing, evaluating, and analyzing data processing systems controlled by general software or software for microcomputers.

There is an increasing trend toward using programmable logic, control software, microprogramming, etc. for administrative and real-time jobs in data processing systems. By the way, conventionally, evaluation tests of such data processing systems rely on partial tracing of the running path of the program.There is no means to organically and efficiently trace a large-scale program under the actual operating environment of the system. Almost none.

An object of the present invention is to eliminate the above-mentioned conventional problems, and to provide a program evaluation test device that makes it possible to efficiently measure running route information of a program in a device under test. be.

Therefore, the feature of the present invention is that in order to test the execution state of the device under test, the instruction read address (value of the program counter) on the address bus and data bus of the device under test is used.
The test equipment sequentially imports instructions and instructions into the test equipment in real time, and the test equipment traces the program running path of the device under test one by one using the instruction read address. It is something that only traces.

Hereinafter, one embodiment of the present invention will be described in detail using the drawings.

FIG. 1 is a configuration diagram of an embodiment of a program evaluation test device of the present invention. In FIG. 1, 1 is a device under test, which is a data processing system controlled by general software or software for microcomputers. 2 is a program evaluation test device of the present invention, and a data import adapter 10. Interface control circuit 1
1. Overlay control circuit 12, static trace control circuit 13, dynamic trace control circuit 14, trace memory control circuits 15 and 16, trace memory 17
．． 18, memory 21, output device 22, etc.

Next, the operation shown in FIG. 1 will be explained. By pulling out the data bus and address bus in the device under test 1 and connecting the adapter 10 to them, the instruction read address, execution instruction group, operand address, operand data, etc. are executed as the program in the device under test 1 runs. It is taken into the test device 2 in a timely manner. The interface control circuit n of the test device 2 sequentially extracts, at a predetermined timing, instruction read addresses and instructions that are particularly important for grasping the program running state of the device under test 1 from among the above information taken in through the adapter 10. , and transferred to the static trace control circuit 13 and the dynamic trace control circuit 14 as trace data. Furthermore, the interface control circuit 1
1 has a command decoding function, and includes an instruction indicating that an overlay operation has occurred in the device under test 1 (for example, a Pot (OUT instruction with a T number) unique to the device under test).
When decoded, the overlay control circuit 12 is notified of the decoding. Note that the overlay operation will be described later.

Static trace control circuit 13, memory control circuit 1
5 and the trace memory 17 are a system for tracing the running U of the program under test in the device under test 1-, and the trace memory 17 has a one-to-one correspondence with the program storage address in the device under test 1. addressed and
Each address consists of 1 bit. Each bit of this trace memory 17 is set to '0' as an initial value by the microcomputer 19. During trace execution, the static trace control circuit 13 reads the instruction read address and the instruction group output from the interface control circuit 11. , detects only the instruction read address indicating the running path of the program at a predetermined timing, and passes the detected instruction read address one by one to the memory control circuit 15.The memory control circuit 15 is connected to the static trace control circuit 13.
Every time an instruction read address is received from a memory, "1" is written to the corresponding address of the trace memory 17, using that address as the write address of the trace memory 17.

FIG. 2 shows an example of the trace format of the trace memory 17. That is, the address A of the trace memory 17
i, j have a one-to-one correspondence with the memory address of the program in the device under test 1, and Ai, j =
1 means that the instruction at the foil memory address in the program under test has been executed. In other words, the trace data in the trace memory 17 represents the running route of the program within the device under test 1.

On the other hand, the dynamic trace control circuit 14, memory control circuit 16, and trace memory 18 are configured to control branch instructions and other specific instructions that indicate the dynamic characteristics of the program, among the execution instructions in the program under test in the device under test 1. This is a system that traces the instruction including its instruction read address. The trace memory 18 is similar to the trace memory 17.
However, each address consists of the number of bits necessary to store trace data consisting of an instruction and an instruction read address, for example, 64 bits (8 bytes). It's true. All zeros are set as initial values by this trace memory 18+j and microcomputer 1'). During trace execution, the dynamic trace control circuit 14 sequentially captures the instruction read address and instruction group output from the interface control circuit 11, temporarily stores it in a buffer register, etc., decodes the instruction, and uses it as a branch instruction or other instruction. , in the case of a predetermined specific instruction, the instruction and its instruction read address are passed to the memory control circuit 16. The memory control circuit 16 is equipped with an address pointer that indicates the write address of the trace memory 18, for example, and when it receives an instruction and an instruction read atomicity from the dynamic trace control circuit 14, the memory control circuit 16 indicates that the address pointer is The instruction and the instruction read address are incorporated as trace data into the indicated address of the trace memory 18, and the address pointer is incremented by 1. Therefore,
For example, if the address pointer of the memory control circuit 16 is set to "0" as an initial value by the microcomputer 19, the dynamic trace data detected by the dynamic trace control circuit 14 is sequentially stored in the memory 18 starting from address 0.

Note that when the trace memo IJ 18 becomes full, the memory control circuit 16 instructs the microcomputer 19 to start up the memory, and thereafter, under the control of the microcomputer 919, the data is output from the dynamic trace control circuit 14. The trace data may be taken in by the microcomputer 19 via the memory control circuit 16 and stored in the auxiliary memory 21. This makes it possible to configure the trace memory 18 with the minimum necessary capacity.

FIG. 3 shows an example of the format of the trace gater stored in the trace memory. In FIG. 3, (a) shows the bit configuration of the first pupil position of the trace memory 18.
It is assumed that it consists of 64 bits (8 bytes). υ）
The figure shows an example of dynamic trace data stored in the trace memory 18.

(b) In the figure, the shaded area represents an unused area.

The above is an operation in the case where the entire running route of the program in the device under test 1 is traced to the trace memory 17, and the entire dynamic trace data is stored in the trace memory 18. On the other hand, depending on the test, it may be sufficient to focus on a predetermined area in the driving program in the device under test 1 and trace the driving route within the area. For example, the static/dynamic trace control circuits 13 and 14 are provided with a first register that specifies the first instruction read address of the corresponding area and a second register that specifies the final instruction read address, and when the test is executed, the interface control The instruction read address output from the circuit 11 is compared point by point with the contents of the first and second registers, and if it matches the first register, then the instructions and instruction read addresses output from the interface control circuit 11 are used as trace data. This can be done by making it valid as , and ending the test when it matches the second register. Addresses to the first and second registers are input from the console and are controlled by the static/dynamic trace control circuit +3 under the control of the microcomputer 19.
+' 14 can be set in the corresponding register. In addition to the functions described above, the microcomputer 19 also has the interface control circuit 11, static/
Dynamic trace control circuit 13°14, memory control circuit +5. ．． It has a start/stop function such as 16 and a function to control the output of obtrusion data in the trace memory 17 and 18 to the output device n.

Next, the overlay operation will be explained. In general, programs include frequently used programs such as management programs and control programs, and programs such as user programs.
It is divided into programs that are used infrequently, but when they are used, they are used continuously for a certain period of time. On the other hand, since there is a limit to the memory capacity lX in the device under test 1, the program storage area of the memory is usually divided into two areas, and frequently used programs are kept resident in one area.
The other area contains programs that are used less frequently (
By importing data from an external file memory, memory is used effectively. The memory area where Durham resides is called the resident area, and the memory area where the stored programs are changed one after another as needed is called the overlay area, and the operation of transferring programs in the overlay area is the overlay operation. It is.

FIG. 4 shows the relationship among the external file memory, the memory within the device under test 1, and the static trace memory 17 of the test device 2 when the device under test 1 has an overlay function. That is, when the device under test 1 has an overlay function, the static trace memory 17 of the test device 2 needs to be in one-to-one correspondence with each module (program module) of the external file memory, as shown in FIG. . The explanation so far corresponds to the case where the program in the resident area of the memory of the device under test 1 is executed, and corresponds to the program that is loaded into the overlay area of the memory of the device under test 1 during overlay operation. Then, it is necessary to separate the trace area of the trace memo January 7th. The operation will be explained below.

When an overlay operation occurs, the device under test 1 receives QI+', which includes the PORT number unique to the device under test, the file memory address of the overlay module, etc.
['Issue the command to replace the program in the overlay memory area. When the test equipment 2 twin tough factory control circuit detects this OUT command, it
C static/dynamic trace control circuit 1 uses an instruction and its successive instruction address as trace data.
3. Overlay control circuit 1 without transferring to 14
Send to 2. The overlay control circuit 12 receives the ['', 01JT command from the interface control circuit 11, and notifies the static trace control circuit 13 that an overlay operation has occurred, and also updates the file memory of the overlay module. The static trace control circuit 13 stores the file memory address given from the overlay control circuit 12, and from then on, the static trace control circuit 13 stores the file memory address given from the overlay control circuit 12.
When the instruction read address is received from 1, the file memory address is also passed to the memory control circuit 15 along with the instruction read address.

The memory control circuit 15 is the static trace control circuit 1
Each time an instruction read address and a file memory address are received from 3, the trace area corresponding to the overlay module in the trace memory 17 is selected with that file memory address, and the instruction read address is placed within the trace area. 1" is written as the write address of . That is, the program running path is traced in the trace memory 17 for each overlay module.

On the other hand, the dynamic trace control circuit 14 (with respect to the overlay control circuit 12 and the interface control circuit 1)
From 1, the receiver passes the received OUT instruction and its instruction read address as is. Dynamic trace control circuit 1
4 decodes the OUT instruction from the overlay control circuit 12, and as a result, it passes the OUT instruction and its instruction read address to the memory control circuit 16 (== as in the case of a branch instruction, etc.) because tracing is necessary. The memory control circuit 16 stores the OUT instruction and its instruction read address at the address of the trace memory 18 indicated by the address pointer at that time.The overlay operation shown in FIG. 3(b).

The display trace shows this. That is, the dynamic trace control circuit 14 and the memory control circuit 16
, the operation of the trace memory 18 is the same as when a branch instruction or the like is detected.

Note that if the device under test 1 does not have an overlay function, the overlay control circuit 12 may be made inactive.

As is clear from the above description, the program evaluation test device according to the present invention provides the following effects.

(1) Facilitates dynamic analysis of the program under test, and makes it clear which areas are tested and which are not.
It is also possible to evaluate the completeness and validity of the test.

(2) By being able to collect data in real time, it becomes possible to perform evaluation tests that do not impair the dynamic characteristics of the program under test.

(3) Since the process of the conventional program testing method becomes clear and is useful for identifying potential defects in the program under test, it is expected that the quality of the program under test will be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing an example of a static trace formant, FIG. 3 is a diagram showing an example of the focus structure of a dynamic trace memory and its trace format, and FIG. 4 is a diagram showing an example of a static trace formant. FIG. 2 is a diagram showing a memory hierarchical structure for explaining overlay operation. DESCRIPTION OF SYMBOLS 1... Device under test, 2... Program evaluation test device, 10... Adapter, 11... Interface control circuit, 12... Overlay control circuit, 13... Static trace control circuit, 14... ...Dynamic trace control circuit, 15.16...Memory control circuit, 1
7.18...Trace memo IJ, +9...Microcomputer, Δ)...Operation vehicle, 21...Auxiliary memory, n...Output device. Agent Patent Attorney Makoto Suzuki °, 1, -, I ゝ・, -1' Figure 1 Figure 2 i Figure 3 (d) (b Figure 4)

Claims (1)

[Claims] 1. In a program evaluation test device that measures the running status of a program of an information processing system (hereinafter referred to as the device under test) under the operating environment of the device under test, an adapter that connects the test device to the device under test; , first and second
a trace memory, a means for extracting an instruction read address or a group of instructions in the device under test that arrives through the adapter, and a means for extracting the extracted instruction read address from the first
means for storing 'l' at the corresponding address of the first trace memory as a write address of the trace memory; A program evaluation test device comprising means for sequentially storing data in a second trace memory, and control means for controlling operations of each of the means.