JPS5892171A - Crt display - Google Patents

Abstract

PURPOSE:To perform individual or mixed display of two kind of pictures, by providing a circuit which switches the scanning system into the sequential scanning or the interlace scanning in response to the presence/absence of a video synchronizing signal of the NTSC standards. CONSTITUTION:When a detection circuit 1 detects a synchronizing signal included in a video signal of the NTSC standards, the circuit 1 outputs a detection signal A of logical 0 and the signal is applied to a horizontal synchronizing signal generating circuit 2 and a vertical counter circuit 3. When a switch SW is a logical 0 of the signal A, the circuit 2 selects the 1st circuit 20, generates a horizontal synchronizing signal HD1 for interlace scanning and when logical 1, the 2nd circuit 21 is selected and a horizontal synchronizing signal HD2 for sequential scanning is generated. A vertical counter circuit 3 reads out picture information stored in a picture memory 4 at the logical 0 of the signal A, this is mixedly displayed in superimposing on the video signal of the NTSC standard, and when no information exists in the memory 4, the signal is singly displayed. At the logical 1, the picture information stored in the memory 4 is displayed through the sequential scanning.

Description

[Detailed Description of the Invention] Is this invention a CI? Regarding display devices, large CI can be used to store images in the image memory and display images of Kugaken or NTmC standards individually, or to display both images in combination.
? This is a turtle related to display decoration.

Conventionally, a Cl display device used in a computer system stores predetermined image information calculated by a computer in the form of an image, and reads the stored image information by sequential scanning synchronized with the rask scan. This will be displayed as the amount of the artist's salary.

However, in recent years, with the spread of burner combinators and home combinators, it has become possible to display images from a computer individually on the same 1ii1, and the N'rlC standard from the Ai welfare video disk drive has become popular. A device capable of displaying a mixture of images from a computer and an image from a computer is desired in order to make economical use of the display device and expand the functionality of the combiator system.

However, the CB that has been used since -? The display device displays images in a progressive scanning manner, while N'rl
Since C-standard CRT display devices display images using an interlaced scanning method, it is not possible to display images using different scanning methods on the same screen.

This invention was made in view of these circumstances, and the image t or NT8C calculated by the objective line combinator.
To provide a CR display device capable of displaying standard images individually or displaying both images in a mixed manner.

For this purpose, the CRT display device f according to the present invention has the following features:
A circuit is provided that switches the scanning method to either sequential scanning or interlaced scanning depending on the presence or absence of the NT@CTi's Eirin synchronization signal.

Hereinafter, the present invention will be explained in detail based on the illustrated embodiments.

The figure is a block diagram showing one embodiment of the present invention. In the figure, the detection circuit 1 detects the synchronization signal included in the NT110 system signal V by comparing the reference voltage corresponding to this synchronization signal and the video signal MID, and detects the synchronization signal. In this case, a detection signal of logic "0" is output. This detection signal is supplied to the horizontal synchronizing signal generating circuit 2 and the vertical counter circuit 3.

The horizontal synchronization signal generation circuit 2 generates a horizontal synchronization signal BDI for interlaced scanning according to the NTi1C standard.
8to and horizontal synchronization signal HD for progressive scanning.

When a detection signal of logic "01" is input as a control signal, the switch 8W is switched to the first @v1zo side to selectively output the horizontal synchronizing signal HDI. When the detection signal M of logic '1' is input, the switch IW is switched to the second circuit 21 side to selectively output the horizontal synchronizing signal HD.The horizontal synchronizing signal (not or IID, ) is supplied to the vertical counter circuit 3. - The vertical counter circuit W11s scans the ii* information stored in the image memory 4 by interlacing scanning when a detection signal of logic 10'' is input. Outputs signals YO to In for image display. That is, the logic '0' detection signal M is inverted by the inverter 3o and supplied to the AND gate 11 and S4.The other input of the AND gate S1 is connected to the horizontal synchronizing signal generating circuit
A horizontal synchronization signal (RDI or HDm) is supplied from
The output thereof is configured to be supplied as a count input signal to the counter 3@ via a NOR gate 33.

, and the other input of the AND gate 34 is a counter 3m.
The configuration is such that the carry signal CARY is supplied, and its output is supplied to the clock input (CP) of the Di1 trip block 31 via the NOR game) 1B.

Therefore, when a detection signal of logic 10m is generated, the horizontal synchronization signal -*BDl for interlaced scanning is input from the horizontal synchronization signal generation circuit l, so that the counter SS receives the signal HD.
, the count value is incremented every time .

In addition, the flip-flop S7 receives a carry signal CART''K which is generated every time the count operation of the counter ss completes one round.
Therefore, the q output is repeatedly inverted between logic "0" and logic "1".

The Q output of the flip-flop S1 is output as the signal YO of the least significant bit (2.) of the line number signal Y indicating the position of the horizontal scanning line in the vertical direction, and the count output signal of the counter 3S is 2 bits (21) ~
The most significant bit (2n) signal is output as signals 11 to 1-.

Therefore, when a logic "0" detection signal is generated, the signal Y indicates the position of an odd or even horizontal scanning line in accordance with the inverting operation of the flip-flop 1110.

That is, during the period in which the tree flop 3T is not set, the signal Y indicates the even-numbered horizontal scanning line position, and the counting operation of the counter 3 completes one cycle, that is, when the scanning of the first field is completed, the signal Y indicates the position of the even-numbered horizontal scanning line. During the period when the knob 37 is set, the signal Y indicates the odd-numbered horizontal scanning line position. Therefore, if the water-scanning light/every K11m information is stored for the picture frame 4, and the signal Y is supplied as an address signal, the image signal at an even address will be signaled during the period when the flip-flop 31 is not set. Then, when the flip-flop 31 is set, only the image signals at odd addresses are sequentially read out.

This makes it possible to store the information in the image memory 4 in synchronization with the synchronization signal of the NTIC standard and generate the nine-picture information. Therefore, by superimposing the read out double flight information on the NTsea rated video signal, the Lsygc standard image and the image corresponding to the image information stored in the image memory 4 can be mixed and displayed.

In this case, when no image information is stored in the image memory 4, only the NTlIC standard image can be displayed independently.

On the other hand, when the vertical counter 3 receives a detection signal of logic "1", it outputs signals YO to Yn for displaying an image by sequentially scanning the ii* information stored in the image memory 4. That is, the detection signal of logic '1#' is the AND gate 32 and 3! Supplied to I. The signal To is supplied from the Q output of the flip-flop 3T to the other input of the AND gate 32, and the output thereof is supplied as a count input signal to the counter 38 via the NOR gate 33. t, AND gate 35 has another input K
A horizontal synchronizing signal HD for the next scan is supplied, and its output is supplied to the clock input (cp) of the 7 rive-flop sT via a NOR gate 36.

Therefore, when a logic "1" detection signal is generated, the flip 70 tube 31 repeats the inversion operation every time the horizontal synchronizing signal HD is generated. That is, the signal y.

repeats logic "01 and 11#" every time the horizontal synchronization signal HD occurs. On the other hand, since the counter 38 signal YO is supplied as a count input signal, the count value is incremented every time the signal YO occurs. As a result, odd-numbered and even-numbered horizontal scanning lines are sequentially indicated every time the signal Yd (horizontal synchronization signal) 10m consisting of signals 0 to Yn is generated.As a result, the image stored in the image memory 4 signal information hd
The gun can be ejected in a sequential scanning manner in synchronization with .

That is, the image information stored in the image memory 4 can be displayed as an image with high resolution by sequential scanning.

In the above embodiment, the counter 38 is configured to generate a carry signal when the counting operation completes one cycle, but it may also be configured to generate a borrow signal.

As is clear from the above description, the CRT display device according to the present invention is equipped with a circuit that switches the scanning method to either sequential scanning or interlaced scanning depending on the presence or absence of the NTl1C standard video synchronization signal. It becomes possible to display an image calculated by a combinator or an image according to the NTIC standard individually, or to display a mixture of both images.

This makes it possible to connect the video signal from the video disc cover or the like to the combiator system, which is extremely effective in expanding the functionality of the computer system.

[Brief explanation of drawings]

The figure is a block diagram showing one embodiment of the present invention. 1... ψ detection circuit, 1... horizontal synchronization signal generation circuit, 3... vertical counter circuit, 4... image memory. Patent applicant: Nippon Musical Instruments Manufacturing Co., Ltd. Agent: Masaki Yamakawa (1 person)

Claims (1)

[Claims] A detection circuit detects the presence or absence of the Eirin synchronization signal of the NTmC standard, and the detection signal of this detection circuit is used as a control input. A horizontal synchronization signal generation circuit that selects and outputs one of the synchronization signals, and a counter that counts the horizontal synchronization signal that is retranslated and output from this horizontal synchronization signal generation circuit and sends out a signal indicating the position of each horizontal scanning line in the horizontal direction. C-tomi equipped with a circuit! Display device.