JPS5917732A - Reducing device of impulsive noise - Google Patents

Abstract

PURPOSE:To obtain a high-quality audio signal, by using a sample holding circuit, a differentiating circuit, a gate circuit, and a variable integrating circuit to interpolate a drop-out part of the signal in the time of an impulsive noise. CONSTITUTION:An input audio signal S1 outputted from a delay circuit 2 is supplied to a sample holding circuit 5, and the signal S1 is given to a control signal generating circuit CSG also, a control signal S2 having a pulse width corresponding to the time when the impulsive noise mixed in the signal S1 exists is generated in the circuit CSG. In the circuit 5, the level just before the time when the impulsive noise mixed in the signal S1 exists is held under the control of the signal S2 during this time. An output S3 is differentiated in a circuit 6 and is sampled and held in a circuit 7 and is sent to a variable integrating circuit 9 through a gate circuit 8. The circuit 9 changes the integration time constant in accordance with an input voltage value to output a signal S7 which interpolates the drop-out part of the impulsive noise, and the signal S7 and the signal S3 are added by a circuit 10.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention is directed to the prevention of moo pulses that are mixed from the outside into the audio signal system of audio equipment, radio receivers, true television receivers, etc. The present invention relates to a pulse noise reduction device that reduces noise in an audible manner.

(Prior art) Pulse noise 1, for example, noise from automobiles or pulses generated in other electrical equipment, is used in the audio signal system of various equipment such as electrical equipment or electronic equipment that has an audio signal system. When sexual noise is mixed in,
It is well known that the quality of audio signals deteriorates.

Conventionally, as a means to reduce the deterioration in audio signal quality caused by the above-mentioned pulse noise mixture, (a) lowering the gain of the signal transmission system during the period in which pulse noise occurs; Or, try to reduce pulse noise by cutting off the signal transmission system (lowering the gain to 70, using a squelch circuit),
(b) The most common method of reducing pulse noise is to maintain the signal level of the signal during the period of pulse noise at the signal level immediately before the period of pulse noise. However, the method of Jl et al.'s (a) and (ol) has the drawback of lacking emotion during the period of pulse noise, and
The problem is that the noise reduction effect cannot be obtained sufficiently even by applying the means described in (a) and (p) above.

By the way, in order to interpolate the missing part of Ushishiru No. 43 during the noise period, after converting the analog Q signal to a digital signal, a correction signal corresponding to the missing part of the signal is created by applying the linear pre-11111 method. Interpolation of the signal during the noise period using the correction signal has been adopted in some digital devices, but implementing it requires the use of complex and expensive circuits. In order to
Such a solution cannot be applied to general audio equipment.

(Problems to be Solved by the Invention) As described above, when the pulse noise mixed in the signal is reduced, signal loss occurs corresponding to the period of existence of the pulse noise. The problem is that even if the pulse noise is reduced, it is not possible to obtain an audio signal of good quality.Also, the interpolation of the missing part of the signal is the final step in solving the two problems in T5 mentioned above. On the occasion of
Requires the use of complex and expensive circuits
The problem is that it is difficult to apply 71 to general audio equipment.

(First Means to Solve the Problem) The present invention is constructed so that the →No.7 pull-hold circuit, the differential circuit, the gate circuit, and the ratio [-C integral time determined by the input voltage value] change. An anag circuit with a simple circuit configuration, such as a variable integration time constant integration circuit, creates a correction signal that can interpolate the missing part of the signal during the period of pulse noise, thereby producing an audio signal with good quality. The present invention provides a device for reducing pulse noise that can be obtained as follows.

(Example) Hereinafter, specific contents of the pulse noise reduction device of the present invention will be described in detail with reference to the accompanying drawings. Reference numeral 1N represents an embodiment of the pulse noise reduction device of the present invention, and in this FIG.
2 is a delay circuit, and C8G is a first control signal generation circuit constituted by a pulse noise detection circuit 3 and a pulse shaping circuit 4. A control signal S2 of pulse 1 corresponding to the period in which pulsed noise exists is generated.

As the pulse noise detection circuit 3 and the pulse shaping circuit 4 in the control signal generation circuit C8G, appropriate circuits may be selected from well-known configurations.

By the way, the control signal S2 generated from the control signal generating circuit C8G needs to correspond correctly to the time axis position of the pulse noise mixed in the audio signal. However, the control signal generation circuit C8G detects -C pulse noise mixed into the input audio signal, and accordingly determines the above-mentioned (corresponding to the period in which the pulse noise exists). Control signal S of response [1]
2 does not occur, there is a predetermined time delay determined depending on the operational characteristic of the first pulse N# detection circuit 3 used, so that the first pulse N# is mixed into the human audio signal. A delay 1.1 having a delay time approximately equal to the time difference between the pulsed noise generated in response to the pulsed noise and the control signal generated in response to the pulsed noise. DJ path 2 supplies input terminal 1 with 1. - Delaying the human audio signal so that the various signal processing performed by the control signal S2 described above is performed correctly at the location where pulsed noise is present in the input audio signal. The input audio signal Sl shown at a in FIG. The location of pulsed noise mixed into the signal SIK,
The position of the control signal S2, which is indicated by b in FIG. 2, exactly coincides with the position on the vertical axis.

In addition, in Fig. 2, time 1 is applied to the input audio signal.
．． -+1. ．． , during the periods from time t3 to t4 and from time t5 to t6, pulse noise N, , N2. It is exemplified as containing N3.

In FIG. 1, the input audio signal S output from the delay circuit 2 is supplied to the first sample-and-hold circuit 5. Each pulse noise N, , N2 . is mixed into the input audio signal S1. The control signal S performs an operation to maintain the signal level of the signal S immediately before the period of existence of N3 for the period of existence of the pulse noise.
It is carried out under the control of 2.

1. Therefore, the first sample hold circuit 5 described above
A signal S3 indicated by C in FIG. The differentiating circuit 6 uses a second differential signal S3 shown as C in FIG.
Output a signal S4 as shown by d in the figure and give it to the second sample and hold circuit 7.

The second sample and hold circuit 7 detects the control signal S2 in the signal S, which is not shown in d of FIG.
The signal level of the signal at the time position immediately before the period of the input audio signal S (same as the period in which the noises N, , N2 and N3 exist) over the period of the pulse width of the control signal S2. Therefore, the second sample hole mill q path 7 supplies a signal S as shown in e of FIG.

Since the gate circuit 8 operates to open the gate only during the period of the control signal S2, the output signal from the gate circuit 8 becomes a signal S6 as shown in f in FIG.

The output signal S6 from the gate circuit 8 is applied to a first variable integration time constant integrator 9, which is configured so that the degree Celsius integration time constant changes according to the input voltage value. At step 9, the input signal S6, which is shown in f of Fig. 2, is integrated and outputted as a correction signal S7, which is shown in g of Fig. 2. Addition circuit 1
Give to 0.

The adding circuit 10 adds the output signal S3 (C in FIG. 2) of the first sample hole 1 circuit 5 described above and the bulge correction signal S7 output from the integrating circuit 9 with a variable integration time constant.
A signal S8 as shown at h in FIG. 2 is output to the output terminal 11.

The signal S8 output to the output terminal 11 is composed of pulse noises N, , N2 . For the signal S3 in which N3 has been removed by the halt operation in the first sample and hold circuit 5, the differentiating circuit 6, the second sample bold circuit 7, the gate circuit 8, and the integrating circuit with a variable integration time constant By adding the correction signal S created by a series of 1-channel operations such as 9, the waveform approximates the waveform of the original audio signal (desired signal) and is audibly unnatural. This means that there are fewer signals.

The correction signal S7 that should not be added to the output signal S3 of the first sample-and-hold circuit 5 by the adder 1O is determined by the period of each pulse noise in the input audio signal S (first → non-pulling pole).・The circuit 5 restores the slope information of the original signal (desired signal) that was lost due to the signal immediately before the pulse noise period of 1. C)
However, such a correction signal S7 is transmitted through the above-mentioned series of (b) circuits: the differentiator circuit 6, the second sample hold circuit 7, the gate circuit 8 and the integrator circuit 9 with a variable integration time constant.
It can be easily created using a series of circuits such as

A concrete explanation of the above points is as follows. The slope information of the original signal (one desired word) that is lost as described above due to the mixing of pulsed noise is similar to the pulsed noise N in a in Fig. 2. In the case where L- is mixed in the relatively flat part of the top of the waveform of the original signal, and in the case where the pulse noise N2 is mixed into the AC axis part of the original signal, that is, the maximum in the original signal, as in the case of In the case where the slope is mixed in the part showing the slope of , second
Pulse noise N, , N2. in a of the figure. The correction signal S to be generated in response to the slope information that is lost from the original signal due to the contamination of N3 is the correction signal S that is used for the portion corresponding to the original signal portion lAf that is mixed with pulse noise N. The 1-ro correction signal is generated at time t1→ in FIG.
As shown in the correction signal 87 shown at t2 (g in Fig. 21), the slope is the gentlest and is used for the part corresponding to the original signal part in which the pulse noise N2 is mixed.
In FIG. 2, the correction signal for
t-Cy correction signal (g in Figure 2), the correction signal is used for the part where the slope is the steepest and corresponds to the original signal part in which the pulse noise N3 was mixed. teeth,
Correction signal St shown at time t, →1 in FIG.
As shown in (g in Figure 2), the slope should be medium and Jl should be Jl.

Then, signals showing different slopes, such as the correction signal S7 shown in the second (g), represent the slope information of the original signal in terms of polarity and voltage value. f) in Fig. 2 is applied to an integrator circuit 9 with a variable integration time constant of -1 (5VC configuration so that the integration time constant changes) according to the input voltage value, and the output signal from the integrator circuit 9 is Obtainable.

Further, as mentioned above, No. 13 S6, which represents the polarity and voltage value calculation (thereby representing the slope information of the original signal), is the output signal 8° from the first sample pole 1 circuit 5 (C in Fig. 2).
) is differentiated by the differentiating circuit 6, and the signal S shows a phase difference of 90 degrees with respect to the original signal (desired signal) and the signal 83.
1 or 11 corresponding to the halt period
I'm there. J: 5 signal 8. Information on the edge of the start position of the cello section in (d) in Figure 2 (the edge of the start position of the upper section becomes a rising edge depending on the direction of the slope of the original signal, 1. - ri, Alternatively, it can be created with a falling edge and a 1 degree angle, and the length of the edge changes depending on the degree of inclination in the original signal.

That is, the output signal 84 from the differentiating circuit 6 (d in FIG.
) to the second sample pole 1 circuit 7, and this second
- Lean pull hole) - Signal S in circuit 7.

In-!・Create the signal S5 in which one section is in the above-mentioned state (Iruma 1 is a halt period in which the signal level of the previous signal S is maintained), and the signal S5 is If only the signal of the bold period in S is extracted by the gate circuit 8, a '+7:C signal S6 as shown in f in FIG. The edge of the starting position of the SE section in the output signal S of V- indicates the slope information of the original signal by the polarity and voltage value.

Integrating the signal S6 as shown in fK in Fig. 2,
As already mentioned, the integration circuit 9 that produces the correction signal S7 as shown in g in FIG. FIG. 3 shows a specific example of the configuration of the i'iJ variable integration time constant integration circuit 9 described above.

In Fig. 3, 9a is an input terminal, 9b is an output terminal, 9
c is the supply terminal of control No. 46, and each end of the control No. 9
The drawing prices of a, 9b, and 9c are shown in Figure 1 for reference.

In Fig. 3 f, AH+ A2 is an operational amplifier, X, ~X
A is to/distor, R, ~R6 are resistors, C is conte/discharge, y, -, -8W are control signal supply terminals 9c
This is a switch whose opening/closing is controlled by a control signal S2 supplied with K, and this switch is not in the open state when the control signal S2 is in the high level state.14) Do the following. Note that this switch bw is an electronic switch.

The collector of transistor X1 is connected to the collector of transistor X3.
The first terminal is connected to the positive power supply +VccK through the resistor R7, and the emitter of the transistor X2 (7) is connected to the positive power supply +Vcc through the resistor R1. , through resistor R5 -CI-Rano/
The :r transmitter of star X3 is connected.

A transistor X is connected to the collector of the transistor X3.
The collector of 4 is connected to the connection point Z, and the non-grounded side of Niconoden→NoC, the input terminal of operational amplifier A2, and the fixed contact F of switch sw are connected to the connection point Z.
The movable ground V of the switch sw is grounded Jl.

1 - The emitter of the transistor
The collector of transistor X2 is connected to the emitter of transistor .

Input terminal 9 of an integrating circuit 9 with a variable integral time constant shown in FIG.
The A1 filter signal sI, which is supplied to the audio signal sI, as described above, is determined at what relative position on the waveform of the audio signal S1 the pulse noise mixed in the audio signal S exists, vc, Therefore, the polarity and peak value of the waves are different.

The signal s6 supplied to the input terminal 9a is amplified by the operational amplifier A and outputted to the point Y, after which it is applied to the bases of the transistors x, , 'x2.

The above-mentioned 1'7 star X and transistor X2 are:
When the voltage at point T is 70 degrees Celsius, the voltage at point Z in a constant current circuit configured with transistors X3, X4, and resistor I(,,R6,
The operation is performed under a standard operating condition in which the voltage is 41 points.

When the voltage at point Y is positive, the voltage at point Y is positive.

As the collector current increases, the voltage drop across the collector resistor R1 of 1 run/star X1 increases, which causes the 17 current of transistor X3 to increase, and
The collector current of the transistor X2 decreases due to the voltage of the positive terminal +a2 at the point Y, and due to the warping, the voltage 1 of the flefter resistor R2 of the transistor X2 becomes smaller, and
When the collector current of star X decreases, the voltage at two points in the constant current circuit becomes the same positive polarity voltage as point Y.

When the voltage at point Y is negative polarity, transformer 7, 7, and X.

-The collector current decreases, and the voltage drop across the left resistor R1 of the transistor X1 decreases.-The collector current of the transistor The collector current of transistor X2 increases due to the voltage, the voltage drop across the collector resistor of transistor X2 increases, and the collector current of transistor The voltage will have the same negative polarity as .

Therefore, the capacitor (fl) connected to two points in the constant current circuit is supplied to the input terminal 9a of the integrating circuit 9.
When the signal S6 to be output is zero, the capacitor C is not charged, and when the signal S6 is positive, the capacitor C is charged at a constant voltage determined according to the voltage value of the signal S6 so that a positive voltage is generated thereon. It is charged with the current value, and furthermore, the signal S
When S6 is of negative polarity, Contin→NoC is charged at a constant current value determined according to the voltage value of signal S6 so that a negative voltage is generated thereto.

By the way, as mentioned above, the fixed contact F and the movable contact ■ of the switch SW are connected to both ends of the capacitor C.
The switch SW is in the off state only during the high rail period of the control signal s2, and the switch SW is in the off state only during the high rail period of the control signal s2.
While charging operation is allowed for :]/denser C, the terminal voltage of C is supplied to the integrating circuit 9 during the pulses of signal S, C, and signal 3. The signal 87 (g in 2nd (2)) has a unipolarity corresponding to the polarity of the signal SIl, and exhibits a change characteristic that gradually increases linearly with a constant slope determined according to the voltage value Vr of the signal SIl. I don't know what to do. The reason why the change in the terminal voltage at the terminal C shows a linear slope characteristic is that the charging to the terminal
This is because the operation is performed using a constant current from a constant current circuit consisting of resistors R, , R, and the like.

The correction signal S7 produced by the integrator circuit 9 with a variable integration time constant and shown in gK in FIG.
The slope of the desired signal during the existence period of the pulsed noise at
The linear interpolation is performed in a U-like manner, so that the first Zumblehole signal S3 and the supplementary IF signal 8□ described above are added in the adder circuit 10. The output signal s8 from J has a waveform similar to the original signal, as shown by h in FIG.

(Effects) As is clear from the above detailed explanation, the pulse noise reduction device of the present invention simply attenuates the gain of the transmission system during the period when pulse noise is mixed. Or, a certain ψ is set so that the level of the signal during the pulse noise period is maintained at the signal level of the signal immediately before the pulse noise, thereby reducing the pulse noise. ．． -Unlike the conventional pulse noise reduction device described above, it also interpolates the signal loss that occurs during the pulse noise period. Pulse noise can be effectively reduced, and the circuit configuration for interpolating missing signals can be realized using a simple analog circuit, resulting in low cost and excellent performance. Moreover, audio equipment can be easily provided.

It should be noted that the pulse noise reduction device of the present invention can be expected to be sufficiently effective when the period during which the pulse noise occurs is narrow f, but when the period during which the pulse noise occurs is wide f. The correction effect may be slightly reduced. However, ignition/ignition noise caused by cars, motorcycles, etc.
iE generated from electrical equipment that has a built-in electric motor,
7: r-pulse noise, pop noise caused by dust or scratches on the disc, 1r-J horn out noise that occurs in the audio signal when the video signal is missing, and other pulses. Effectively applied to sexual noise tl'
Of course.

[Brief explanation of drawings]

FIG. 1 is a diagram of the implementation of the pulse noise reduction device 6 of the present invention for a deaf person;
FIG. 3 is a circuit diagram of an example of a variable integral 1 ('f constant integral 1 ('') path configuration.

Claims (1)

[Scope of Claims] 1. Means for detecting pulsed noise in an input audio signal containing pulsed noise and generating a control signal having a pulse [I] corresponding to a period in which the pulsed noise occurs. , the above-described control signal is generated in response to the pulsed noise in the input signal, and the time difference between the control signal and the corresponding pulsed noise is approximately equal to the time difference between the control signal and the corresponding pulsed noise. Delay circuits with equal delay times
C. means for delaying an input audio signal containing pulsed noise to a first Zambrepoort circuit in which said control signal is supplied as a sampling pulse; means for applying an output signal to an adder circuit and a differentiating circuit; means for applying an output signal of said differentiating circuit to a second Zambreholt circuit to which said control signal is supplied as a sampling pulse; The output signal of the second sample halt circuit is as described above in 1. - means for applying the control signal to a gate circuit which is supplied as a gate signal; means for applying the correction signal to an integrating circuit to obtain a correction signal; and applying the correction signal to an addition circuit to add the correction signal and the output signal of the first pull-bold circuit; Pulse noise reduction device comprising means for outputting an audio signal with further reduced pulse noise. Pulse noise reduction device 3 according to range 1 is an integrator circuit with a variable integration time constant, which is capable of obtaining an integrated output signal with a polarity corresponding to the polarity of the signal input to the output device 1. A device for reducing pulse noise according to claim 1, which uses a device configured as a device.