JPS59220077A - Inverter with abnormality detecting circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Advantageous Field of the Invention] The present invention relates to an inverter equipped with an abnormality detection circuit that can detect mainly phase loss in the inverter output.

[Background of the invention]

Conventionally, the presence or absence of output current of each phase of an inverter has been detected to detect a failure of the inverter itself, a break in the electric path from the inverter to the load, or a failure of the load device.

However, such an inverter in which a detector is provided for each phase of the output not only has a complicated configuration, but also has a tendency for the detector itself to become high (ilfi).

Furthermore, recently, as proposed in Utility Model Application Laid-Open No. 57-175586 (Utility Application No. 56-58615), there is also a system that performs open phase detection by detecting the current supplied to an inverter inverter. However, in such a device, when the output voltage and output frequency of the inverter change significantly, it tends to become difficult to accurately detect an open phase state.

[Purpose of the invention]

Therefore, the present invention provides an inverter equipped with an abnormality detection circuit that can accurately detect abnormal operating conditions such as phase loss or output cutoff.

[Summary of the invention]

That is, the inverter device of the present invention includes a current detection circuit that detects a current waveform supplied to an inverter of the inverter device, a waveform shaping circuit that shapes the detection signal of this current detection circuit into a binary code, and this waveform shaping circuit. The apparatus is provided with an abnormality detection circuit that outputs an abnormality signal when the change period of the binary code outputted from the circuit exceeds a predetermined change period.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to FIG.
K will explain. In the figure, 1 is a three-phase AC power supply, 2 is a forward conversion device, 16 is an inverse conversion device, 3 is a first current detector (resistor) inserted in the electric circuit connecting the forward conversion device 2 and the inverse conversion device 16, C is a ballast capacitor. 5 is a frequency setting circuit for setting the output frequency of the inverter device;
6 is a v/f converter that outputs a pulse train of a frequency according to the voltage value set in the frequency setting circuit 5; 7 is a V/f converter that receives the pulse train of the v/f converter 6 and the set value of the frequency setting circuit 5; A three-phase waveform shaping circuit for distributing a pulse train into three phases at a set period, 10
receives the three-phase command signal from the six-phase waveform shaping circuit 7, and outputs a combination of base signals of the transistors Q1 to Q6 for controlling conduction of the transistors Q, to Q6 constituting the inverter 6. This is the base drive circuit. Furthermore, D.

-D are flywheel diodes connected in parallel to transistors Q1-Q, respectively. Such an inverter has already been known in the past, and the PWM (Pu1se
By performing Width Modulation) control, for example, the induction motor IM connected to this
3-phase power is supplied to the

Now, when such an inverter is operating normally, a waveform as shown in FIG. 2(a) is observed by the current detector 3. This waveform is six times the output frequency of the inverter and has a negative component due to the presence of load impedance.

In addition, when the inverter is in an abnormal state (-phase loss), this waveform changes as shown in Figure 2 (a+), and the change period becomes longer.Therefore, in this embodiment, changes in this waveform period are monitored. By doing so, it is possible to determine whether it is normal or abnormal. 4 is a filter circuit for extracting the main component in the detection signal from the current detector 3, and 5 is a filter circuit for further adding binary values to the output signal of the filter circuit 4. This is a waveform shaping circuit that shapes the waveform into a square wave of the same number.The output waveforms of the filter circuit 4 and the waveform shaping circuit 5 are shown in Fig. 2, (b), (c), and (e).
, (f) (where (θ1. (f) is the waveform at the time of phase loss). 9 is an abnormality detection circuit that inputs the signals of the waveform shaping circuit 8 and the v/f converter 6 and outputs an abnormal signal; 11
is an alarm output circuit that receives an abnormal signal and drives a lamp or buzzer for indicating an abnormality.

Next, the detailed configuration and operation of the abnormality detection circuit 9 will be explained with reference to FIGS. 3 and 4. 12 is the UP counter (
The output of the waveform shaping circuit 8 is received at the reset terminal R, and at the H level of this signal, the reset state m,
It counts the pulse train of the V/t converter 6 input from the clock terminal C at L level. 13
14 is a coincidence circuit that issues a coincidence signal when the count number of the UP counter 12 reaches a predetermined value; 14 is a hold circuit that issues a continuous abnormal signal upon receiving the coincidence signal; 15
is a reset circuit that resets the abnormal signal of this hold circuit 14.

That is, FIG. 4 shows the normal and abnormal output signals (A) of the waveform shaping circuit 8 at a frequency of 70, the output signal (B) of the (CI, ■/f converter 6), and the output signal (B) at the same wave number F2 (1'l< F
Normal/abnormal output signal (D) of the waveform shaping circuit 8 of t)
, (f), V/t converter O output signal (E)
As shown respectively, the period of the square waveform output signal obtained by the waveform shaping circuit 8 and the v/f converter 6
The period of the pulse train output from the inverter has a constant relationship with the output frequency of the inverter. For this reason, in order to determine an abnormality in the inverter, for example, an open phase state, the L level period T, , T of the square wave attracted by the waveform shaping circuit 8 is
, can be measured based on the output frequency of the V/t converter 6.

Here, □・N−T ont N=fout@T In addition, T , (TguT,, T=M11N=
Count number fOut: ■/f Converter output frequency T: Open-phase waveform discrimination time In the embodiment, the reset terminal R of the UP counter 12
If the number of pulse trains input from the clock terminal C to the ■/f converter 6 becomes four or more while the signal is maintained at L level, the matching circuit 16 operates and a matching signal is output. There is. That is, in the embodiment, when normal operation is continued, the number of pulse trains of the ■/f converter 6 output during the period in which the output signal of the waveform shaping circuit 8 remains at the L level is 2 to 6; If the count advances beyond three, the matching circuit 15 may be set so that a matching signal is output.

With such a configuration, even if the output frequency and output voltage of the impark change, an abnormality (open phase) state of the inverter can be reliably detected.

Normally, the current detector 3 (current transformer OT can also be incorporated) is often built-in to detect the overload condition of the inverter, so in the example button, only a small amount is required. The present invention can be realized at low cost by adding additional circuit components.

In the above embodiment, the pulse period of the /f converter 6 is used to determine the L level period T1 of the output signal of the waveform shaping circuit 8, but this is different from the same L level during normal operation. A data table is provided in which the relationship between the period T and the output frequency of the inverter is stored in advance, and by using this data table, the waveform shaping circuit 8
The device may be configured to determine that an abnormal state exists when the L level period T1 of the output signal exceeds a stored value.

Further, in the embodiment, the L level signal of the waveform shaping circuit 8 was used, but it is also possible to perform similar detection using the H level signal, and the ratio of the periods of the L level signal and the H level signal can also be used. It is also possible to consider abnormal operation when this ratio is out of a predetermined range.

Furthermore, in the embodiment, in order to improve the noise resistance, the hold circuit 14 can be configured to output an abnormal signal only when the coincidence signal is output from the coincidence circuit 13 a plurality of times in succession. In addition, when the inverter starts or suddenly accelerates or decelerates, the detection waveform detected by the current detector 3 may become unstable, so in such cases, it is recommended to stop the operation of the abnormality detection circuit 9. It is also possible to combine a suitable timer circuit or an AND circuit.

Although the embodiment device has been described with respect to an inverter with equal width PWM control, the present invention uses unequal width PWM control or PAM (Pulse Amplitude)
The inverter for modulation control can also be implemented in a similar manner.

〔Effect of the invention〕

As is clear from the above description, the present invention provides an inverter device including an inverter, a current detection circuit that detects a current waveform supplied to the inversion device, and a binary code for the detection signal of the current detection circuit. and an abnormality detection circuit that outputs an abnormal signal when the change period of the binary code outputted from the waveform shaping circuit exceeds a predetermined change period range, According to the present invention, abnormal operating conditions of an inverter can be accurately detected.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining the configuration of one embodiment of the present invention, FIG. 2 is a diagram for explaining waveforms at various locations in the block diagram of FIG. 1, and FIG. FIG. 4 is a block diagram for explaining the main parts of FIG. 1 in detail, and FIG. 4 is a diagram for explaining the operation of the embodiment. ,9
... Abnormality detection circuit, 16... Inverse conversion device agent
Patent Attorney Akio Takahashi No. 1 Sono No. 2

Claims (1)

[Claims] In an inverter device including an inverter, a current detection circuit that detects a current waveform supplied to the inverter, a waveform shaping circuit that shapes a detection signal of the current detection circuit into a binary signal, and a waveform shaping circuit that An inverter equipped with an abnormality detection circuit that outputs an abnormal signal 1'' when the change period of the output binary signal exceeds a predetermined change period.