JPS5924308A - Program timer - Google Patents

Abstract

PURPOSE:To select easily an output mode of the load to be driven simultaneously in response to the state of the load, by providing a means, etc. to set plural set step storage regions and store the set time information to each storage region. CONSTITUTION:A means, etc. are provided to store the set time information to plural set step storage regions. For instance, the power is supplied to a microprocessor CPU1 through a constant voltage circuit 13, and driving and time pulses are supplied via a clock pulse generating circuit 2. At the same time, the interruption signals are transmitted in a prescribed cycle via an interruption signal generating circuit 3. Then both simultaneous and sequential start modes are selected and set by means of a mode selection switch 12, and the data on numeric characters, channel number, etc, are fed to the CPU1 via a keyboard 4 to write and erase the program data to the memory of the CPU1. The prescribed displays are carried out at a time display part 5, a day display part 6 and a set output monitor 7 via an automatic/manual changeover circuit 9, an output monitor 10 and a relay part 11.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of the Invention The present invention relates to a program timer that controls driving or stopping a plurality of loads at preset times.

(B) Background of the Invention In general, when a program timer is used to control the drive/stop of a plurality of loads, a plurality of channels)v (multiple loads) may be controlled to be driven at the same time.

In this case, the output timing from the program timer to the heavy load is to simultaneously send out the a@ channel output, so if the load to be driven and controlled is a heavy load, the contract power may be exceeded or the line voltage may drop instantaneously. There is a problem in that it may adversely affect other devices. In order to solve this problem, it is desirable to slightly shift the output sending timing for each channel.

On the other hand, in the case of a light load, there is no need to take the trouble to shift the output sending timing for each channel as described above. Therefore, even when driving and controlling a plurality of loads at the same time, it would be advantageous if it were possible to select simultaneous output or staggered output for each channel depending on the load situation.

(c) Purpose of the Invention The purpose of the present invention is to provide a program timer that allows the user to easily select the output mode to the loads to be driven simultaneously according to the load situation (light load, single load). be.

B) Structure and Effect of the Invention In order to achieve the above object, the program timer of the present invention has a plurality of setting step storage areas.

Load number/drive/to be controlled in each setting step storage area
Means for storing data indicating stoppage and set time information such as day of the week, hour and minute, means for generating a one-hour signal, and means for receiving the time signal from the time signal generating means and storing current time information such as day of the week, hour and minute. a counting means; and a comparison means for comparing each set time information and the current time information to confirm whether the image information matches.

and means for outputting a signal for controlling a corresponding load based on the matching output of the comparing means, and a plurality of loads are set to be driven at the same time.

The output means is comprised of a switching means for switching between outputting the plurality of drive signals from the output means to each load simultaneously or sequentially outputting them with a predetermined timing shift.

According to the program timer of the present invention, when driving and controlling multiple loads at the same time, each load is driven at the same time depending on the load condition, or the timing is sequentially shifted for each load channel to drive the loads. This selection can be easily made by operating the switching means.

(E) Description of Embodiments The present invention will be explained in further detail with reference to embodiments shown in the following nine drawings.

FIG. 1 is a block diagram of a program timer showing one embodiment of the present invention. In the figure, 1 is a 4-bit 1-chip C-MOS microprocessor (hereinafter referred to as CPU).
It is. This CPU 1 executes a timer function based on a processing flow described later. A clock pulse generation circuit 2 is connected to the CPU 1 to provide driving pulses and time pulses.

Further connected is an interrupt signal generating circuit 6 for interrupting the CPU 1 at a predetermined period (for example, 2.5 m5).

The keyboard 4 is connected to the CPUI and is used to input various data in addition to numbers, days of the week, and channel numbers to the CPUI. ] (RAM)
Write program data to.

Or delete and modify that data.

The output of the CPU 1 is displayed on the time display section 5. It is added to and displayed on the day of the week display section 6 and setting output monitor 7.

The time display section 5 consists of a 4-digit numerical display that displays the current time, channel number at program setting, and on/off.
Displays off data and program time. The day of the week display section 6 is composed of seven light emitting elements corresponding to each day of the week, and displays the current day of the week as well as the day of the week when the program is set. The setting output monitor 7 is composed of light emitting elements for four channels, and displays the channel number set at the time of program setting.

The weekly program switch 8 is connected to the L CPU 1, which is made up of seven switches corresponding to each day of the week. When the weekly program switch 8 is in the "auto" state, the channel load is controlled according to the program for that day. but.

When in the "off" state, load control of all channels is disabled.

CPU1 and output monitor 10. An automatic/manual switching circuit 9 is provided between the relay parts 11. Automatic/manual switching circuit 9
is "on" or "off" for each channel.

It is configured with a changeover switch that can switch between "auto" and CP only when each channel is set to "auto".
The output of the UI is transmitted to the output monitor 10 and the relay part 11, and when it is "in", the relay part 11 is forcibly driven regardless of the output of the CPU. The relay part 11 consists of four pieces that operate (drive) or stop the equipment connected to this program timer, and the output monitor 10 consists of light emitting elements that display the operating status of the load equipment for each channel. It is something.

Reference numeral 12 denotes an output transmission mode selection switch circuit, and when this circuit is in an on state, a plurality of outputs are simultaneously transmitted at the same time (this case is referred to as simultaneous activation mode). Conversely, when it is in the OFF state, multiple outputs that should be output at the same time are sequentially sent out every second (this case is referred to as sequential startup mode), that is, the output sending mode selection switch circuit 1
2 selects and sets the simultaneous start mode and sequential start mode.

Note that 13 stabilizes the voltage E from the main power supply.

A constant voltage circuit 14 that supplies power to the CPU 1 is a battery that backs up the circuit and allows the CPU 1 to execute processing operations even when the main power supply is turned off.

2 and 6 show a front view and a back view of the external case of the GLODARAM timer shown in FIG. 1, and the same numbers as those shown in FIG. 1 indicate corresponding parts, respectively. 15 is an output terminal.

CPU1j of the program counter in the above embodiment:.

It has a built-in RAM as a storage means, and the RAM of the penis is the 4th one.
As shown in the figure, there is a stack and working storage area M1, a calculation register N1. N2 and the data store area M2 of the setting step. Here, in the data store area M2 of the setting step, 25 setting steps can be set, and the storage area for each setting step includes day of the week, hour and minute data, channel) vf;, data, and output on/off. The data shown is stored.

The data storage arrangement for one setting step is shown in Figure 5, where 1 minute data is stored in 4 bits (4 bits at address n) bl to b4, and 1 minute data is stored in 6 bits (b1 to b) at address n+1. The 4 bits of data at address n+2 contain data at the 1 o'clock position, the 2 bits bl and b2 at address n+6 contain data at the 10 o'clock position, and the 402 bits b6 and b contain the channel/v& data at address n+4. Day of the week data is set and stored in the five bits b1 to b3, and data indicating output on/off is set and stored in the bit b4 at the same address. Data T for each setting step
13). Then set the setting step address to 1 (ST
14), then it is determined whether all 25 setting step data have been searched (ST15). Initially, the judgment was NO, so 1
Next, it is determined whether the time and day of the week data in setting step 1 match the current time (ST16).

In the above example, since they match, next the channel/L/A data stored in setting step 1 is used to determine the channel. For setting step 1, the channel/'5 data is OO, which means channel/L/&1. This channel/L/ku1 is stored as data 0001 in the accumulator Acc in the CPU1 (STI 7). Subsequently, in 5T18, it is determined whether the setting output is on or off by referring to the b4 bit at address n+4 in setting step 1. In this case, it is 1 (on), so move to 5T19, perform the logical sum of data 1010 at address 9N1 and data 0001 in accumulator Ace, and store the resultant data 1011 at address N1 (ST2
2). Then, add 1 to the set step address, set it to 2 (5T23), and jump to 5T15.

This time, for setting step 2, the operations from ST15 onwards will proceed. In the above example, did you search all the data for 5T15? If the determination is NO, the process moves to 5T16 and it is determined whether the time and day of the week match.

This moves to YES-cST17 and sets the channel/'! in step 2. Channel/v2 is determined from data 01.

The data 0010 is loaded into the accumulator Acc. Next, it is determined whether the data is on (ST18).

Setting step 2 address n'+4 pick l-b 4 is 0 (
Off) and the judgment is No, so set step 1
Unlike the case of , the content of accumulator Ace is 001
0 is inverted to obtain 11o1, which is added to the accumulator Ac.
It is reset to e (ST20). Next, the data 1011 at address N1 and the data 1101 in the accumulator Acc are ANDed (ST21), and the resultant data 1001 is
Restore to address 1 (ST22). Then add +1 to the setting step address to make it 6 (5T23), S T
Jump to 15.

Subsequently, regarding setting step 3, the operations from ST15 onward proceed. Also in the case of this setting step 5, the judgment N of 5T15
O, Did the time and day of the week of 5T16 match? Judgment: YES
Move on to Tona5ST17. At 5T17, determine the channel/I/L6 from the channel data 10 of setting step 5, and set the data [110, O'i in the accumulator Ace. Next, in the setting step B, bit b4 at address n'+4 is 1, is it on data? Make a YES decision 5
T18), as in the case of setting step 1, take the logical sum of the data at address N1 and the accumulator Ace (ST1
9). Since this data on the station side is 1001 and 0100, the resultant data is 1101. This data is stored at address N1 (ST22). Then add +1 to the setting step address to make it 4 (5T23), S T 15
Jump to.

Thereafter, the operations from 5T15 onward are repeated until all searches of the setting step data are completed, but in the example shown here, the setting time and day of the week match the current time and day of the week only in the 6 steps in the table above. . Therefore, did the time and day of the week match on 5T16? Judgment is No 5ST23
Then, only the step address continues to advance.

(15) When all data searches are completed, 5T15 to 5T
Jump to 24. In ST24, the data at address N1 is compared with the output register to determine whether the current output matches the stored content at address N1. If they match, it means that the output has already been sent, so a timer check and timer processing are performed in 5T25 and ST26, and the process moves to ST27.

In the above example, the store data at address N1 is 1101° and the data in the output register is 1010, so there is a mismatch.The output output mode switching selection circuit 12 is checked here to determine whether the mode is simultaneous startup mode or sequential startup mode. ST
29), if set to simultaneous startup mode, N
Load data 1101 at address 1 into accumulator Ace (5T30).

Furthermore, the data 1 stored in the accumulator Ace is 71-
101 is outputted via an output register.

If sequential startup mode is set in ST29,
It is determined whether a one-second timer (built in the CPUI) is activated (ST32). 1 (14) If the second timer is not activated, first check the current output state, that is, the contents of the output register ID10'17-1i-
The data is loaded into the umulator Acc, and the logical product of this loaded data and the data at address N1 is executed as the primary.

The result is stored at address N2 (Sr33). In the above example, 1000 is obtained as the AND of data 1010 and data 1101 at address N1. This data indicates the channel whose output is still on.

Next, an exclusive OR operation is performed on addresses N1 and N2, and the result is stored in accumulator Ace (Sr3
4). In the above example, it is an exclusive OR of 1101 and 1000, and 0101 is obtained as the result data. This data is data indicating the channel whose output is turned on.

In other words, it shows that channels 1 and 5 are turned on.

Following 5T34, it is determined whether the green bit (first bit) of accumulator Acc is 1 (5T35).

If it is 1, move to 5T36 and restore the contents of address JN2 +00O1 to location N2. In the above example, the 2° bit is 1 and 1000 is stored at address N2, so N2
1000+0Ocz=1ocz is newly stored at the address. Next, start the 1 second timer (5T37), then data 1001'ff at address N2: accumulator ic
5T38), and then transfer it to accumulator A.
The data 1001 of ce is outputted through the output register (Sr31). This will cause channel 1 to be turned on first. Channel 2 remains on, channel 3 remains off, and channel 4 remains on.

After that, after 5T27 key flag = 1 or 9NO, 5T1
Return from 2 to 5T24. In Sr14, the data 1101 at address N1 and the contents 1001 of the output register do not match, so the judgment is NO and the process moves to S'T 29.However, since it is a sequential startup mode, the judgment in this step is also No and the process moves to 5T32 to see if the 1-second timer has started. It will be judged. This judgment is YES, so next check whether 1 second has passed (Sr
25). If 1 second has not passed, jump to 5T27.

Similar processing is repeated until one second has elapsed.

When Sr15 determines that 1 second has elapsed, the 1-second timer is reset and its contents are cleared at the same time (Sr2
6).

The operation after Sr16 is Sr17 judgment No-, 5T12 judgment No->ST24 judgment No-, 5T29 judgment No-, 5
Proceed with T32. Is the 1 second timer on Sr12 running? Since the one second timer is stopped at 5T26 as described above, this determination is No and the process moves to psT33. In this step, the data 1001 of the output register and the data 1101 of address N1 are ANDed and the resultant data 1001 is stored in the accumulator Ace! Stored at address 1IN2. Next, data 110 at address N1 in Sr14
1 and the data 1001 at address N2 are exclusive-ORed and the resulting data 0100 is stored in the accumulator Acc.

Data stored in accumulator A Cc 0100
The 2° bit of id, the 21st bit is O and the 22nd bit is 1, so is the 2° bit of 5T35 = 1? The judgment is No,
If the determination is No at 5T39 and YES at 5T41, the process moves to 5T42. In 5T42, N2 soy sauce content 10
01 and 010[1 are added.

As a result, the value 1101 is stored again at address N2. Next, move to Sr17 and start the 1 second timer.

Furthermore, data at address N2 is transferred to accumulator A at 5T38.
Cc, and at 5T31, the data 1101 of the accumulator Ace is transferred to the output register for output processing. This causes channel zv3 to appear after 1 second following channel/L/1.
This means that it is also turned on. (Channel/L/2 is off, channel V4 remains on) After the output processing in Sr31, the process returns to Sr14 through the NO-decision of 5T27 and NO of 5T120, but here, the current output register contents 1101 and Since the data at address l'J1 match, the judgment in this step is YES, and when 1 second elapses, the 1 second timer is stopped and its contents are cleared. 5T25.5
T26), then proceed to ST27.

As described above, when turning on (driving) multiple load channels at the same time, by setting in advance whether to start simultaneously or sequentially, it is possible to turn on multiple outputs at exactly the same time, or some timing time (e.g. 1
They can be turned on sequentially by staggered intervals (seconds). Whether to start them simultaneously or sequentially may be determined depending on the weight (or weight) of the load.

Note that the 1-second timer in the above embodiment counts the number of interruptions every 2.5 mS, and when it counts 400 times, it means that exactly 1 second has passed after activation, so it can be easily implemented. Repeat this count 800 times.

By changing the number to 1,200 times, a 2-second timer and a 6-second timer can be obtained instead of a 1-second timer, so the shift timing width in sequential activation can be arbitrarily changed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a program timer showing an embodiment of the present invention, FIG. 2 is a front view of the external gate of the program timer shown in FIG. 1, FIG. 6 is a back view of the same, and FIG. 1st
The program timer shown in the figure is a diagram showing the storage area arrangement of the RAM built into the CPU (which constitutes the program timer shown in the figure).
FIG. 6 shows the bit arrangement of the output register; FIG. 7 is a processing flow diagram of the program timer interrupt routine shown in FIG. 1; Figure 8 (Figure 8-1, Figure 8-...
) is a processing flow diagram of the same normal routine. 1: CPU, 2: Clock pulse generation circuit. 6: Interrupt generation circuit, 4: Keyboard. 5: Time display section, 6: Day of the week display section, 7: Setting output monitor, 8: Weekly program switch. 9: Automatic/manual switching circuit, 1o: Output monitor. 11: Relay part, 12: Mode selection switch circuit,
16: Constant voltage circuit, 14: Battery. 15: Output terminal. Patent Applicant Tateishi Electric Co., Ltd. Agent Patent Attorney Shigeru Nakamura 2nd Tier R Award 3 Figure No. 5 Figure 4 Item 5 Item 0 Anti-Kaya Figure 7 Bud Figure 8-E Procedural Amendment (Method) 1982 November 8th, Mr. Commissioner of the Japan Patent Office1, Indication of curvature Patent No. 154661 of 19822 Title of invention Program timer 3? Relationship with the depiction of neutrasexuality in the name of the person who is applying for the patent Address: 10, Hanazono Tsuchido-cho, Ukyo-ku, Kyoto City Name:
(294) Tateishi Electric Co., Ltd. Representative Takao Tateishi 4 Agent 6 Subject of supplement fl) 1l Column 7 for detailed explanation of the invention in the JIal document
Time is counted in the divine inner world (Sr1). After this time count, the routine returns to the normal processing routine shown in FIG. At this point, the setting nutep data shown in the following table is set in the RAM in the CPU 1. The current time is 12:64 on Monday, and the output status at that time is 1 channel...off, 2 channel...on,
3 channels...off, 4 channels...on (output V
The operation of the normal processing routine will be explained by taking as an example the case where the contents of the register are 1010). Following the initial setting of 5T11 after the start of operation.

Claims (1)

[Claims] (1) A program for controlling multiple loads to drive or stop at preset times. 1. Means having a plurality of setting step storage areas and storing load numbers to be controlled, data indicating drive/stop, and setting time information such as day of the week, hour and minute in each setting step storage area;
means for generating a time signal, means for receiving the time signal from the time signal generating means and counting current time information such as day of the week, hour and minute, and comparing each of the set time information and the current time information. and a means for outputting a signal for controlling a corresponding load based on how the comparison means matches. When a plurality of loads are set to be driven at the same time, it is possible to switch between outputting the plurality of drive signals from the output means to each load at the same time or sequentially outputting high forces shifted by a predetermined timing. A program timer characterized in that it is comprised of means as follows.