JPS5951667A - Frame frequency converting circuit of television signal - Google Patents

Abstract

PURPOSE:To simplify the constitution, by operating an original input signal with the same clock signal without interpolation of a signal between scanning lines. CONSTITUTION:An analog telecvision signal converting a frame frequency f1 is converted into a digital signal via an input terminal 1 and applied to a memory 4. Picture elements of NXf1/f2 among total number of pictures N of the stored signal are read out equivalently and a television signal in a frame frequency f2 is reproduced. Thus, the circuit is activated without interpolation of the signal between scanning lines.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a television signal frame frequency conversion circuit;
In particular, the present invention relates to a circuit system for converting a signal with a low frame frequency, such as a television signal based on the PAL system, into a television signal with a high frame frequency.

Currently, the frame frequency of television signals differs depending on the television signal system, and some of them, such as the above-mentioned PAL system, have a frame frequency as low as 25H1/sec. When a reproduced image from a television signal with such a low frame frequency is received in a bright room, it may cause flicker due to human visual characteristics, which may be bothersome.

However, when the frame frequency becomes 30 Hz/sec or more, flicker disappears.

On the other hand, regarding the method of converting one television signal to a television signal of another standard.

It is conventionally known as a format converter for television signals (for example, "Recent TV standard format converter", Journal of the TV Society, Vol. 29, No. 10). In this conventional device, the television system before conversion and the television system after conversion each have their own standards, such as the NTSC system and the PAL system, so both must satisfy strict standards.

Therefore, there are many difficulties in the configuration of the device, such as the need to provide a slight difference in the writing and reading frequencies of the field memory or frame memory that records the screen of the television signal.

It is also necessary to perform interpolation in conjunction with the conversion of the number of scanning lines.

However, if the purpose is simply to increase the frame frequency to prevent flicker based on the frame frequency, this is a problem within the receiver, and there is a degree of freedom in the form of the converted signal. Therefore, problems in device configuration due to the above-mentioned standard conversion are not necessarily reduced. Further, there is no need to store all portions of the television signal that are not displayed on the screen in the memory.

In order to obtain images with less flicker, the present invention
/ signal frame frequency conversion circuit with a simple configuration.

In order to achieve the above object, the frame frequency conversion circuit for television signals of 11 according to the present invention has a frame frequency of 1
The main feature is that the television signal of frequency f2 is configured to be reproduced in the storage device from the television signal of □.

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a general explanatory diagram for frame frequency conversion, and the line A above shows a part of the frame frequency of 25 Hz/sec, and the AI
+ A2 + A3...A5 are numbered. Line B at the bottom of the figure is a frame frequency of 30Hz/sec.
, the second frame A2 is repeated twice, and B1. B2. B2', B3...The songs are numbered and shown as a period of 6 frames.

Now, write frame A1 to memory and write this to B1.
(A method for shortening the time B compared to the time A1 will be described later).

Similarly A2. Write each B2 and read the line now.

This Toki, frame A2. It is assumed that settings are made so that writing and reading of frame B2 are completed synchronously. At the time of read frame 82', focusing on an arbitrary address, when frame B2 is continuously output, since frame A3 has not been written yet, the information of frame A2 will be read. Then, the information of frame A3 is read out at the time of frame B3. Repeat the same operation below. In this way, the frame AI HA 2 + A
3 +A4. Information on A5 is frame B I T 82
+82'.

B3. B4. B, and the frame number is converted.

FIG. 25 is a diagram showing the configuration of an embodiment of a television signal frame frequency conversion circuit according to the present invention.

An analog television signal whose frame frequency is to be converted passes through an input terminal 1, and a portion thereof is converted into a digital signal by an A/D converter and is applied to a memory 4.

FIG. 3 is a diagram for explaining the relationship between the number of pixels or the capacity of the memory when writing to and reading from the memory.

Now, as an example, a television signal based on the PAL system will be described as an original signal with a low frame frequency (A1, A2, . . . in FIG. 1).

As shown in the outer frame of FIG. 3, one frame of the PAL television signal can be expressed as 625 scanning lines and 966 pixels on each scanning line.

Therefore, the total number of pixels in one frame is 625×966. Some of the total number of pixels are not directly related to image reproduction, so there are 5 pixels as shown in the inner frame of Figure 3.
If there are 75 scanning lines and only 875 pixels of the - scanning line are used for reading, the total number of pixels and the number of pixels used for reading are as follows.

In other words, if the original human power signal is recorded over an area of 625 x 966 pixels, and then read out by synchronizing the pixel frequency for 575 x 875 pixels, the time will be exactly 5/6 times as shown in Figure 1. The action is performed.

Note that at this time, it is not necessary to prepare a memory device for 625×966 pixels, but it is sufficient to prepare a memory device for 575×875 pixels. Furthermore, it is obvious that the synchronization signal does not necessarily have to be prepared.

In this case, it is possible that only the address circuit operates and there is no corresponding memory cell, or that the address circuit is inactive.

Returning now to FIG. 2, the original input television signal is applied to timing circuit 6. The timing circuit 6 separates and extracts the vertical synchronization signal. Then, do this once every 5 frames.
(corresponding to the time 1=0 in FIG. 1), the counters of the write address circuit 70 and the read address circuit 8 are reset. Further, a horizontal synchronizing signal is extracted by a conventionally known method, and a sampling clock for 966 times of scanning is generated by a conventionally known phase pull-in circuit or the like. This clock is applied to each address circuit 7°8 and D
/A converter 5. Thereafter, the counter of the write address circuit 7 counts 625x966 as a synchronization, and the counter of the read address circuit 8 performs writing and reading of information in the range shown in FIG. 3 using 575x875 as a synchronization. As a result, Freno frequency conversion is performed in the time relationship as shown in FIG.

According to the present invention, the same clock signal is used from the A/D conversion circuit 3 that digitizes the human input signal to the I)/A conversion circuit 5 of the converted signal. Operates without interpolation between signal scanning lines,
The advantage is that it is extremely easy to print.

Note that it is clear that the present invention is not limited to the first embodiment, and for example, the following modifications can be considered.

In the above embodiment, each frame of the converted television signal has exactly the same number of pixels and is perfectly periodic, but even if it is not necessarily perfect, some margin period is provided, etc. It is also possible to shift within a range that does not cause any problems in terms of design or circuitry.

The memory includes not only a completely random memory but also various modifications, such as switching delay lines in blocks, as long as it is possible to input and output signals as in the above-mentioned embodiments.

[Brief explanation of drawings]

FIG. 1 is a time chart diagram for detailed explanation of the present invention, and FIG.
The figure is a block diagram of an embodiment of a television signal frame frequency conversion circuit according to the present invention, and FIG. 3 is a diagram for explaining the number of pixels in the above embodiment. 1...Input terminal, 2...Output terminal, 3...A/D
Conversion circuit, 4... Frame memory, 5... D/A converter, 6... Synchronization signal separation circuit, 7... Write address circuit, 8... Read address circuit. Figure 1 Figure 3 Figure A cable

Claims (1)

[Claims] 1. A frame frequency conversion device for a television signal, comprising: a storage device; and a television signal having a frame frequency f1; and means for reproducing a television signal having a frame frequency f2.