JPS60103728A - Transistor input circuit - Google Patents

Transistor input circuit

Info

Publication number
JPS60103728A
JPS60103728A JP58211932A JP21193283A JPS60103728A JP S60103728 A JPS60103728 A JP S60103728A JP 58211932 A JP58211932 A JP 58211932A JP 21193283 A JP21193283 A JP 21193283A JP S60103728 A JPS60103728 A JP S60103728A
Authority
JP
Japan
Prior art keywords
terminal
transistor
level
resistor
input circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58211932A
Other languages
Japanese (ja)
Inventor
Haruhiko Nishi
西　春彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP58211932A priority Critical patent/JPS60103728A/en
Publication of JPS60103728A publication Critical patent/JPS60103728A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/0823—Multistate logic

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To constitute a tri-state input circuit with minimum number of components by connecting an input terminal to a node via a resistor and connecting an output teminal to a collector of two NPN transistors (TRs) respectively. CONSTITUTION:When the input terminal 1 is at L level, an NPN TR13 is interrupted, an NPN TR12 is conducted and the output terminal 14 goes to an L level. When the terminal 1 is at H level, the TR12 is disconnected, the TR13 is connected and the output terminal 6 goes to H level. In applying a voltage between a voltage applied to a power terminal 8 and a voltage of the 1st reference power supply 2, i.e., an M level to the terminal 1, the TRs 12, 13 are disconnected both and no output appears at the terminals 4 and 6.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は半導体集積回路に最適なトランジスタ入力回
路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a transistor input circuit most suitable for semiconductor integrated circuits.

〔従来技術〕[Prior art]

半導体集積回路などにおいては、主に端子叡の削減のた
めに２条件設定の信号を多重して、ＬレベルおよびＨレ
ベルのホカ、このＬレベルとＨレベルの中間にＭレベル
を設定して、１つの入力端子を用いて、３種のレベルを
与えることが行なわれる。このような３値入力を判別す
る入力回路を第１図に示す。すなわち、第１図は従来の
トランジスタ入力回路を示す回路図である。同図におい
て、１は入力端子、２は第１基準電圧源、３は第１電圧
比較器、４は第１出力端子、５は第２基準電圧源、６は
第２電圧比較器、７は第２出力端子である。In semiconductor integrated circuits, etc., signals with two condition settings are multiplexed mainly to reduce terminal interference, and the M level is set between the L level and the H level, and the M level is set between the L level and the H level. Three levels are provided using one input terminal. FIG. 1 shows an input circuit for determining such three-value input. That is, FIG. 1 is a circuit diagram showing a conventional transistor input circuit. In the figure, 1 is an input terminal, 2 is a first reference voltage source, 3 is a first voltage comparator, 4 is a first output terminal, 5 is a second reference voltage source, 6 is a second voltage comparator, and 7 is a This is the second output terminal.

この構成によるトランジスタ入力回路は入力端子１に入
力する３値入力に対し、第１出力端子４の出力レベルお
よび第２出力端子Ｔの出力レベルにより判別するもので
ある。The transistor input circuit having this configuration discriminates a three-value input input to the input terminal 1 based on the output level of the first output terminal 4 and the output level of the second output terminal T.

しかしながら、従来のトランジスタ入力回路では電圧比
較器を２個使用するため、回路規模が大きくなる欠点が
あった。However, since the conventional transistor input circuit uses two voltage comparators, it has the disadvantage of increasing the circuit scale.

〔発明の概要〕[Summary of the invention]

したがって、この発明の目的は最小限の回路素子数で構
成することができるトランジスタ入力回路を提供するも
のである。Therefore, an object of the present invention is to provide a transistor input circuit that can be configured with a minimum number of circuit elements.

このような目的全達成するため、この発明は一方の端子
が電源端子に接続される第１抵抗と、コレクタがこの第
１抵抗の他端に接続され、エミッタが第１ノードに接続
され、ベースに第１基準電圧が印加されるＮＰＮ　トラ
ンジスタと、−万の端子がアースに接続される第２抵抗
と、エミッタが第１ノードに接続され、コレクタが第２
抵抗の他端に接続され、ベースに第２基準電圧が印加さ
れるＰＮＰ　）ランジスタとを備え、入力端子は前記Ｊ
１ノードに接続され、第１出方端子は前記ＮＰＮトラン
ジスタのコレクタに接続され、第２出方端子は前記ＰＮ
Ｐトランジスタのコレクタに接続されるものであシ、以
下実施例を用いて詳細に説明する。To achieve all of these objects, the present invention provides a first resistor having one terminal connected to a power supply terminal, a collector connected to the other end of the first resistor, an emitter connected to the first node, and a base connected to the first resistor. a second resistor whose emitter is connected to the first node and whose collector is connected to the second node;
A PNP transistor connected to the other end of the resistor and having a base applied with a second reference voltage, the input terminal being connected to the J
1 node, a first output terminal is connected to the collector of the NPN transistor, and a second output terminal is connected to the collector of the NPN transistor.
It is connected to the collector of the P transistor, and will be explained in detail below using an embodiment.

〔発明の実施例〕[Embodiments of the invention]

第２図はこの発明に係るトランジスタ入力回路の一実施
例を示す回路図である。同図において、８は電源端子、
９は一方の端子が入力端子１に接続され、他方の端子が
第１ノード１ｏに接続される抵抗、１１は一方の端子が
電源端子８に接続され、他方の端子が第１出力端子４に
接続される第１抵抗、１２はコレクタがこの第１抵抗１
１の他方の端子に接続され、エミッタが第１ノード１゜
に接続され、ベース・がｍ１基準電圧源２に接続される
ＮＰＮ　）ランジスタ、１３はエミッタが第１ノード１
０に接わ１：され、コレクタが第２出力端子６に接続き
れ、ベースが第２基準電圧源４に接続されるＰＮＰ　）
ランジスタ、１４は一方の端子がアースに接続され、他
方の端子がこのＰＮＰ　）ランジスタ１３のコレクタに
接続される第２抵抗である。FIG. 2 is a circuit diagram showing an embodiment of the transistor input circuit according to the present invention. In the figure, 8 is a power supply terminal;
9 is a resistor whose one terminal is connected to the input terminal 1 and the other terminal is connected to the first node 1o, and 11 is a resistor whose one terminal is connected to the power supply terminal 8 and the other terminal is connected to the first output terminal 4. The first resistor connected, 12, has its collector connected to this first resistor 1.
1, the emitter is connected to the first node 1°, and the base is connected to the m1 reference voltage source 2; 13 is an NPN transistor whose emitter is connected to the first node 1
0, the collector is connected to the second output terminal 6, and the base is connected to the second reference voltage source 4)
The transistor 14 is a second resistor having one terminal connected to ground and the other terminal connected to the collector of this PNP transistor 13.

次に、上記構成によるトランジスタ入力回路の動作につ
いて説明する。まず、入力端子１がＬレベル、すなわち
接地に近い電圧の場合には、ＰＮＰトランジスタ１３は
遮断され、ＮＰＮ）ランジスク１２は導通し、コレクタ
電流が流れる。このため、第１抵抗１１に電圧降下が生
じ、第１出力端子４はＬレベルになる。次に、入力端子
１がＨレベル。Next, the operation of the transistor input circuit having the above configuration will be explained. First, when the input terminal 1 is at L level, that is, at a voltage close to ground, the PNP transistor 13 is cut off, the NPN transistor 12 is conductive, and a collector current flows. Therefore, a voltage drop occurs across the first resistor 11, and the first output terminal 4 becomes L level. Next, input terminal 1 goes to H level.

すなわち電源電圧に近い電圧の場合には、ＮＰＮ）ラン
ジスタ１２は遮断され、ＰＮＰトランジスタ１３は導通
してコレクタ電流が流れる。このため、第２抵抗１４に
電圧が発生し、第２出力端子６はＨレベルになる。次に
、入力端子１に、電源端子８に印加する電圧と第１基準
電圧源２の電圧との間の電圧、すなわちＭレベルが印加
したとき、ＮＰＮトランジスタ１２およびＰＮＰ　）ラ
ンジスタ１３が共に遮断状態になる。このため、第１出
力端子４は電源電圧となシ、第２出力端子は接地電圧と
なる。このように、入力端子１がＬレベルのときには第
１出力端子４に出力が得られ、入力端子１がＨレベルの
ときには第２出力端子６に出力が得られ、入力端子１が
Ｍレベルのときには第１出力端子４および第２出力端子
６には共に出力がないことになる。That is, in the case of a voltage close to the power supply voltage, the NPN transistor 12 is cut off, and the PNP transistor 13 is turned on, allowing a collector current to flow. Therefore, a voltage is generated in the second resistor 14, and the second output terminal 6 becomes H level. Next, when a voltage between the voltage applied to the power supply terminal 8 and the voltage of the first reference voltage source 2, that is, the M level is applied to the input terminal 1, both the NPN transistor 12 and the PNP transistor 13 are in a cut-off state. become. Therefore, the first output terminal 4 becomes the power supply voltage, and the second output terminal becomes the ground voltage. In this way, when input terminal 1 is at L level, an output is obtained at first output terminal 4, when input terminal 1 is at H level, output is obtained at second output terminal 6, and when input terminal 1 is at M level, output is obtained at first output terminal 4. Both the first output terminal 4 and the second output terminal 6 have no output.

第３図はこの発明に係るトランジスタ入力回路の他の実
施例を示す回路図である。同図において、１５．１６お
よび１７はそれぞれ直列に接続された抵抗であシ、この
抵抗分圧により、第１基準電圧および第２基準電圧を発
生することができる。なお、動作については第２図の動
作と同様であることはもちろんである。FIG. 3 is a circuit diagram showing another embodiment of the transistor input circuit according to the present invention. In the figure, 15, 16 and 17 are resistors connected in series, and the first reference voltage and the second reference voltage can be generated by voltage division of these resistors. Note that the operation is of course similar to that shown in FIG. 2.

なお、第２基準電圧源４の代シに第１基準電圧源２を共
用してもよいことはもちろんである。It goes without saying that the first reference voltage source 2 may be used in place of the second reference voltage source 4.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したように、この発明に係るトランジス
タ入力回路によれば最小の素子で３値入力の回路を構成
することができるので、半導体集積回路に用いることが
できる効果がある。As described in detail above, according to the transistor input circuit according to the present invention, a three-value input circuit can be constructed using the smallest number of elements, so that the transistor input circuit can advantageously be used in a semiconductor integrated circuit.

【図面の簡単な説明】 第１図は従来のトランジスタ入力回路を示す回路図、第
２図はこの発明に係るトランジスタ入力回路の一実施例
を示す回路図、第３図はこの発明に係るトランジスタ入
力回路の他の実施例を示す回路図である。 １・・・・入力端子、２・・・・第１基準電圧源、３・
・・・第１電圧比較器、４・・・・第１出力端子、５・
・・・第２基準電圧源、６・・・・第２電圧比較器、７
・・・・第２出力端子、８・・・・電源端子、９・・・
・抵抗、１０・・・・第１ノード、１１・・・・第１抵
抗、１２・・・・ＮＰＮ　トランジスタ、１３・―・−
ＰＮＰ　）ランジスタ、１４・・・・第２抵抗、１５．
１６および１７・・・・抵抗。 なお、図中、同一符号は同一または相当部分を示す。 代理人　大岩増雄 第１図 第２図 第３図 手続補正書（自発） １、事件の表示　特願昭５８−２１１９３２号２、発明
の名称　トランジスタ入力回路３、補正をする者 代表者片山仁へ部 ４、代理人 （１）　明細書の特許請求の範囲の欄 （２）明細書の発明の詳細な説明の欄　旭（１）明細書
の特許請求の範囲を別紙の通シ補正する。 （２）明細書第３頁第１４行気１５行の「入力端子は前
記第１ノードに接続され」を「入力端子は前記第１７−
ドに抵抗を介して接続され」と補正する。 （３）明細書第５頁第８行〜１０行の「、電源端子８〜
との間の電圧」を次の文の通シ補正する。 「第１基準電圧源２の電圧と第２基準電圧源４の電圧と
の間の電圧１ 以上 別　紙 ［一方の端子が電源端子に接続される第１抵抗と、コレ
クタがこの第１抵抗の他端に接続され、エミッタが第１
ノードに接続され、ベースに第１基準電圧が印加される
ＮＰＮトランジスタと、一方の端子がアースに接続され
る第２抵抗と、エミッタが第１ノードに接続され、コレ
クタが第２抵抗の他端に接続され、ベースに第２基準電
圧が印加されるＰＮＰ）ランジスタとを備え、入力端子
は前記第１ノードに抵抗を介して接続され１．第１出力
端子は前記ＮＰＮＩ−９ンジスタのコレクタに接続され
。 第２出力端子は前記ＰＮＰ　）ランジスタのコレクタに
接続されることを特徴とするトランジスタ入力回路。」 以上[Brief Description of the Drawings] Fig. 1 is a circuit diagram showing a conventional transistor input circuit, Fig. 2 is a circuit diagram showing an embodiment of a transistor input circuit according to the present invention, and Fig. 3 is a circuit diagram showing a transistor input circuit according to the present invention. FIG. 3 is a circuit diagram showing another example of the input circuit. 1... Input terminal, 2... First reference voltage source, 3...
. . . first voltage comparator, 4. . . first output terminal, 5.
...Second reference voltage source, 6...Second voltage comparator, 7
...Second output terminal, 8...Power terminal, 9...
・Resistor, 10...first node, 11...first resistor, 12...NPN transistor, 13...-
PNP) transistor, 14...second resistor, 15.
16 and 17...Resistance. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Agent: Masuo Oiwa Figure 1 Figure 2 Figure 3 Procedural amendment (voluntary) 1. Indication of case: Japanese Patent Application No. 58-211932 2. Title of invention: Transistor input circuit 3. To Hitoshi Katayama, representative of the person making the amendment. Part 4, Agent (1) Claims column of the specification (2) Detailed explanation of the invention column of the specification Asahi (1) Amend the claims of the specification in a separate document. (2) In page 3, line 14, line 15 of the specification, "the input terminal is connected to the first node" is replaced with "the input terminal is connected to the 17th node".
This is corrected by connecting the terminal to the terminal via a resistor. (3) "Power terminals 8 to 10 on page 5 of the specification, lines 8 to 10.
Correct the voltage between the following sentences. ``Voltage 1 between the voltage of the first reference voltage source 2 and the voltage of the second reference voltage source 4'' the emitter is connected to the other end, and the emitter is connected to the first
an NPN transistor connected to the node and having a first reference voltage applied to its base; a second resistor having one terminal connected to ground; an emitter connected to the first node and a collector connected to the other end of the second resistor; a PNP transistor connected to the first node and having a second reference voltage applied to its base; the input terminal is connected to the first node via a resistor; 1. A first output terminal is connected to the collector of the NPNI-9 transistor. A transistor input circuit characterized in that a second output terminal is connected to a collector of the PNP transistor. "that's all

Claims (1)

【特許請求の範囲】[Claims] 一方の端子が電源端子に接続される第１抵抗と、コレク
タがこの第１抵抗の他端に接続され、エミッタが第１ノ
ードに接続され、ベースに第１基準電圧が印加されるＮ
ＰＮ　）ランジスタと、一方の端子がアースに接続され
る第２抵抗と、エミッタが第１ノードに接続され、コレ
クタが第２抵抗の他端に接続され、ベースに第２基準電
圧が印加されるＰＮＰ　）ランジスタとを備え、入力端
子は前記第１ノードに接続され、第１出力端子は前記Ｎ
ＰＮ　）ランジスタのコレクタに接続され、第２出力端
子は前記ＰＮＰ　）ランジスタのコレクタに接続される
ことを特徴とするトランジスタ入力回路。a first resistor having one terminal connected to a power supply terminal, a collector connected to the other end of this first resistor, an emitter connected to a first node, and a first reference voltage applied to a base of the N
PN ) transistor, a second resistor with one terminal connected to ground, an emitter connected to the first node, a collector connected to the other end of the second resistor, and a second reference voltage applied to the base. PNP ) transistor, an input terminal is connected to the first node, and a first output terminal is connected to the N
A transistor input circuit, wherein the transistor input circuit is connected to a collector of a PNP transistor, and a second output terminal is connected to the collector of the PNP transistor.
JP58211932A 1983-11-09 1983-11-09 Transistor input circuit Pending JPS60103728A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58211932A JPS60103728A (en) 1983-11-09 1983-11-09 Transistor input circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58211932A JPS60103728A (en) 1983-11-09 1983-11-09 Transistor input circuit

Publications (1)

Publication Number Publication Date
JPS60103728A true JPS60103728A (en) 1985-06-08

Family

ID=16614063

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58211932A Pending JPS60103728A (en) 1983-11-09 1983-11-09 Transistor input circuit

Country Status (1)

Country Link
JP (1) JPS60103728A (en)

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