JPS60187046A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS60187046A JPS60187046A JP59042617A JP4261784A JPS60187046A JP S60187046 A JPS60187046 A JP S60187046A JP 59042617 A JP59042617 A JP 59042617A JP 4261784 A JP4261784 A JP 4261784A JP S60187046 A JPS60187046 A JP S60187046A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- lead
- semiconductor device
- ceramic
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/63—Vias, e.g. via plugs
- H10W70/635—Through-vias
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
- H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
fa) 発明の技術分野
本発明は、半導体装置に係り、特に、半導体チップを搭
載するビングリッドアレイ型セラミックパッケージにお
ける外部導出リード端子の導出構造およびその製造方法
に関す。DETAILED DESCRIPTION OF THE INVENTION fa) Technical Field of the Invention The present invention relates to a semiconductor device, and particularly to a lead-out structure for external lead terminals in a bin grid array type ceramic package on which a semiconductor chip is mounted, and a manufacturing method thereof.
(bl 技術の背景
最近の半導体装置は、半導体チップのパッシベーション
技術が向上してモールドパッケージのものが多いが、高
信顛度を必要としたり特殊環境下で使用されるものにつ
いては、依然としてメタルパッケージやセラミックパッ
ケージなどを用いて気密封止したものが重用な地位を占
めている。中でも、集積度が高く大形電子計算機などに
使用される半導体装置は、導出する端子数が多いことや
半導体チップからの導線長を短くすることもあって、角
形にしその周辺から端子を導出したセラミックパッケー
ジが主流をなしている。4本発明に係る半導体装置に使
用するピングリッドアレイ型セラミックパッケージは、
リード端子をマトリックス状に配列して角形パッケージ
本体の底面から略垂直に導出したパッケージであって、
半導体チップの高集積化に伴い、該パッケージの小型化
ないしリード端子数の増大化が望まれている。(bl Technology background) Recently, many semiconductor devices are packaged in molds due to improvements in passivation technology for semiconductor chips, but devices that require high reliability or are used in special environments are still packaged in metal packages. Semiconductor devices that are hermetically sealed using ceramic packages, etc., occupy an important position.In particular, semiconductor devices with a high degree of integration and used in large-scale computers, etc. have a large number of lead-out terminals, and semiconductor chips In order to shorten the length of the conductor wires from the pin grid array type ceramic package used in the semiconductor device according to the present invention, the mainstream is a ceramic package in which the terminals are led out from the periphery of a rectangular shape.
A package in which lead terminals are arranged in a matrix and led out approximately perpendicularly from the bottom surface of a square package body,
As semiconductor chips become more highly integrated, it is desired that the package be made smaller or have an increased number of lead terminals.
(C) 従来技術と問題点
第1図は従来のビングリッドアレイ型セラミックパッケ
ージを使用した半導体装置の一例の側面図(a)とその
構造を示す側断面図(b) (C1で、1は絶縁基体、
11〜13は絶縁層、2a、2bは配線、3はスルーホ
ール、4は端子座、5はリード端子、6は固定材、7は
蓋、Aは半導体チップ、Bはワイヤ、plは端子ピンチ
をそれぞれ示す。(C) Prior art and problems Figure 1 is a side view (a) of an example of a semiconductor device using a conventional bin grid array type ceramic package, and a side sectional view (b) showing its structure. insulating base,
11 to 13 are insulating layers, 2a and 2b are wiring, 3 is a through hole, 4 is a terminal seat, 5 is a lead terminal, 6 is a fixing material, 7 is a lid, A is a semiconductor chip, B is a wire, pl is a terminal pinch are shown respectively.
図(a)図示の半導体装置におけるパンケージの構造は
凡そつぎの通りである。即ち、図(b1図示において、
セラミックの絶縁基体lは、半導体チップAの底面を接
地導出する配線2aとAの回路を導出する複数の配線2
bとが設けられ、個々の配線2a、2bはそれぞれ個別
に、スルーホール3を介して、絶縁基体1の底面周辺に
おけるリード端子5の導出位置に配置された導電性の端
子座4に接続されてなっている。この部分の詳細は図(
c)図示のようであり、端子座4には、例えばコバール
や42合金(42%ニッケルー鉄)などからなる線状の
リード端子5が、絶縁基体1の底面に対し略垂直に導出
するように、例えば銀鑞など導電性の固定材6で固定さ
れ、そして、露出している導体部分に例えば金などのめ
っきが施されている。The structure of the pancage in the semiconductor device shown in FIG. 3(a) is approximately as follows. That is, in Figure (b1 illustration),
The ceramic insulating substrate l has a wiring 2a that leads the bottom surface of the semiconductor chip A to ground and a plurality of wirings 2 that lead out the circuit of A.
b, and each wiring 2a, 2b is individually connected to a conductive terminal seat 4 disposed at a lead-out position of a lead terminal 5 around the bottom surface of the insulating base 1 via a through hole 3. It has become. The details of this part are shown in the figure (
c) As shown in the figure, a wire lead terminal 5 made of, for example, Kovar or 42 alloy (42% nickel-iron) is attached to the terminal seat 4 so as to be led out approximately perpendicularly to the bottom surface of the insulating base 1. , for example, is fixed with a conductive fixing material 6 such as silver solder, and the exposed conductor portion is plated with, for example, gold.
ここで、絶縁基体1は、最初は三層の絶縁層11〜13
に分けられたグリーンシートで、11には配線2aと端
子座4とを、また12には配線2bを導電性物質である
例えばタングステンペーストなどで印刷し、スルーホー
ル3の位置に明けられた孔に同様な導電性物質を充填し
た後、積層焼成一体化して作られている。Here, the insulating base 1 initially has three insulating layers 11 to 13.
The wiring 2a and the terminal seat 4 are printed on 11, and the wiring 2b is printed on 12 with a conductive material such as tungsten paste, and a hole is made at the position of the through hole 3. It is made by filling a similar conductive material and then laminating and firing them into one piece.
半導体装置の構成は、このパッケージに半導体チップA
をグイボンディングにより固定し、配線2bの端部と半
導体チップA表面の端子とをワイヤボンディングにより
ワイヤBで接続し、蓋7を被せシールしてなっている。The configuration of the semiconductor device is that semiconductor chip A is placed in this package.
are fixed by wire bonding, the ends of the wiring 2b and the terminals on the surface of the semiconductor chip A are connected by wire B by wire bonding, and the lid 7 is covered and sealed.
この半導体装置を実装する場合は、例えばプリント配線
基板などの接続ランドにある孔に端子5を挿入し、通常
はんだで固定接続する。このため、パッケージにおいて
は、絶縁基体1に対するリード端子5の固着強度が充分
に大きいことが必要である。When this semiconductor device is mounted, the terminals 5 are inserted into holes in connection lands of a printed wiring board, for example, and fixed connections are usually made with solder. Therefore, in the package, it is necessary that the adhesion strength of the lead terminals 5 to the insulating substrate 1 be sufficiently large.
リード端子5は端子座4に固定されているため、端子座
4には成る程度の大きさが必要になり、相隣るリード端
子5の間隔即ち端子ピンチを小さくすることは、端子座
4の大きさによって制約される。Since the lead terminal 5 is fixed to the terminal seat 4, it needs to be large enough to fit the terminal seat 4, and reducing the interval between adjacent lead terminals 5, that is, the terminal pinch, Limited by size.
従ってこの構成でなるパッケージを使用した半導体装置
においては、端子ピッチplは通常100ミル(2,5
4mm)であるが、上記事情によりこの端子ピッチp1
を極端に小さくすることが困難で、半導体チップの集積
度向上に伴って望まれる小型化ないしリード端子数の増
大化が制限される欠点を有する。Therefore, in a semiconductor device using a package with this configuration, the terminal pitch pl is usually 100 mils (2.5 mils).
4mm), but due to the above circumstances, this terminal pitch p1
It is difficult to make it extremely small, and it has the drawback that miniaturization or an increase in the number of lead terminals, which is desired as the degree of integration of semiconductor chips increases, is restricted.
ldl 発明の目的
本発明の目的は上記従来の欠点に鑑み、ビングリッドア
レイ型セラミックパッケージの相隣るリード端子の間隔
を小さくすることが可能な構造を有する半導体装置およ
びその製造方法を提供するにある。ldl OBJECTS OF THE INVENTION In view of the above-mentioned conventional drawbacks, an object of the present invention is to provide a semiconductor device having a structure capable of reducing the distance between adjacent lead terminals of a bin grid array type ceramic package, and a method for manufacturing the same. be.
te+ 発明の構成
上記目的は、半導体チップを搭載するパッケージの絶縁
基体がセラミックであって、該基体から外部に導出する
り一ド端子が該セラミック基体の焼成に耐えうる金属か
らなり、その一部が該基体内に植え込まれていることを
特徴とする半導体装置によって、また、半導体デツプを
搭載するパッケージのセラミック基体の焼成に先立ち、
該基体の内部配線に繋げて該基体に穿った孔に導電性物
質を充填すると共にリード端子の一部を挿入し、しかる
後、該基体を該導電性物質と共に焼成する工程を有する
ことを特徴とする半導体装置の製造方法によって達成さ
れる。te+ Structure of the Invention The above object is such that the insulating base of a package on which a semiconductor chip is mounted is made of ceramic, and the lead terminal led out from the base is made of a metal that can withstand the firing of the ceramic base, and a part of the insulating base is made of ceramic. is implanted in the substrate, and prior to firing of the ceramic substrate of the package carrying the semiconductor depth,
It is characterized by having the step of connecting to the internal wiring of the base body, filling a hole bored in the base body with a conductive substance, inserting a part of the lead terminal, and then firing the base body together with the conductive substance. This is achieved by a method of manufacturing a semiconductor device.
前記リード端子は、その一部が前記基体内に植え込まれ
ているため、該基体比対して充分な固着強度を有し、然
も、従来例における端子座を必要としないので、相隣る
該リード端子の間隔を極めて小さくすることが可能であ
る。Since the lead terminal is partially implanted in the base, it has sufficient adhesion strength relative to the base, and does not require the terminal seat in the conventional example, so It is possible to make the interval between the lead terminals extremely small.
(fl 発明の実施例
以下本発明の実施例を図により説明する。全図を通じ同
一符号は同一対象物を示す。(fl Embodiments of the Invention Hereinafter, embodiments of the present invention will be described with reference to the drawings. The same reference numerals indicate the same objects throughout the drawings.
第2図は本発明の構造によるビングリッドアレイ型セラ
ミックパッケージを使用した半導体装置の一実施例の側
面図(a)とその構造を示す側断面図(b) (C)で
、1aは絶縁基体、5aはリード端子、plは端子ピッ
チをそれぞれ示す。FIG. 2 is a side view (a) of an embodiment of a semiconductor device using a bin grid array type ceramic package according to the structure of the present invention, and side sectional views (b) and (C) showing the structure, where 1a is an insulating substrate. , 5a are lead terminals, and pl is the terminal pitch.
図(a1図示の半導体装置におけるパッケージの構造は
第1図図示のパッケージと略同様で、その相違点はリー
ド端子の材料と固定方法にある。即ち、図Tb)図示に
おいて、セラミックの絶縁基体1aは、半導体チップA
の底面を接地導出する配線2aとAの回路を導出する複
数の配線2bが設けられ、個々の配線2a、 2bはそ
れぞれ個別に、絶縁基体1aの周辺におけるリード端子
5aの導出位置に配置されたスルーホール3に接続され
てなっている。この部分の詳細は図(C)図示のようで
あり、リード端子5aは、線状の高融点金属例えばタン
グステンからなり、絶縁基体1aの底面側からスルーホ
ール3に植え込まれて、絶縁基体1aの底面に対し略垂
直に導出し、そして、露出している導体部分に例えば金
などのめっきが施されている。The structure of the package in the semiconductor device shown in FIG. is semiconductor chip A
A wiring 2a for grounding the bottom surface of the circuit A and a plurality of wirings 2b for leading out the circuit A are provided, and each of the wirings 2a and 2b is individually arranged at the lead-out position of the lead terminal 5a around the insulating base 1a. It is connected to through hole 3. The details of this part are as shown in FIG. The conductor is led out approximately perpendicularly to the bottom surface of the conductor, and the exposed conductor portion is plated with, for example, gold.
ここで、絶縁基体1aは、第1図図示の絶縁基体1と略
同様に、最初は三層の絶縁層11〜13に分けられたグ
リーンシートで、11には配線2aを、また12には配
線2bをS電性物質である例えばタングステンペースト
などで印刷し、スルーホール3の位置に明けられた孔に
同様な導電性物質を充填した後、積層焼成一体化して作
られるが、該焼成に先立ちスルーホール3にリード端子
5aを挿入しておき、その状態で焼成することによって
リード端子5aの固定も同時に行っている。この焼成は
高温(約1500℃程度)で行われるが、リード端子5
aは、材料をタングステンにしであるので劣化するこは
ない。Here, the insulating substrate 1a is a green sheet that is initially divided into three insulating layers 11 to 13, substantially the same as the insulating substrate 1 shown in FIG. The wiring 2b is printed with an S conductive material, such as tungsten paste, and the holes made at the positions of the through holes 3 are filled with a similar conductive material, and then the layers are laminated and fired to form an integrated structure. The lead terminals 5a are first inserted into the through holes 3 and fired in this state, thereby fixing the lead terminals 5a at the same time. This firing is performed at a high temperature (approximately 1500°C), but the lead terminal 5
A is made of tungsten, so it will not deteriorate.
半導体装置の構成は、第1図図示の場合と同様に、この
パフケージに半導体チップAをグイボンディングにより
固定し、配線2bの端部と半導体デツプA表面の端子と
をワイヤポンディングによりワイヤBで接続し、蓋7を
被せシールしてなっている。The structure of the semiconductor device is similar to that shown in FIG. 1, in which the semiconductor chip A is fixed to this puff cage by hard bonding, and the ends of the wiring 2b and the terminals on the surface of the semiconductor depth A are connected with wires B by wire bonding. They are connected, covered with a lid 7, and sealed.
この構成でなるビングリッドアレイ型パフケージを使用
した半導体装置においては、リード端子5aの太さを0
.2fiにすれば、端子ピッチp2を25ミル(0,6
35m■)にすることが可能になり、160個のリード
端子5aを絶縁基体1aの周辺に二列に配列した場合、
絶縁基体1aの大きさは約15龍角でよい。因に、前述
のように第1図図示の構成で端子ピッチp1が100ミ
ル(2,54龍)の場合は、80個のリード端子5を二
列に配列するのに、絶縁基体lの大きさは約33龍角が
必要であり、仮に、端子ピッチp1を50ミル(1,2
7龍)にしても約16關角になり、上記に対して、絶縁
基体lの大きさは略近くなるがリード端子数は半分に過
ぎない。In a semiconductor device using a bin grid array type puff cage having this configuration, the thickness of the lead terminal 5a is set to 0.
.. If you set it to 2fi, the terminal pitch p2 will be 25 mils (0,6
35 m), and when 160 lead terminals 5a are arranged in two rows around the insulating base 1a,
The size of the insulating substrate 1a may be approximately 15 square meters. Incidentally, as mentioned above, if the terminal pitch p1 is 100 mils (2.54 mm) in the configuration shown in FIG. Approximately 33 dragon angles are required, and if the terminal pitch p1 is set to 50 mils (1,2
7), it will be about 16 angles, and the size of the insulating base l will be almost similar to the above, but the number of lead terminals will be only half.
然も、リード端子5aの固定は、前記焼成において同時
に行うので、製造行程が従来より単純化する利点もある
。However, since the lead terminals 5a are fixed at the same time as the firing, there is an advantage that the manufacturing process is simpler than the conventional method.
(g) 発明の効果
以上に説明したように、本発明による構成によれば、ピ
ングリッドアレイ型セラミックパッケージの相隣るリー
ド端子の間隔を小さくすることが可能な構造を有する半
導体装置およびその製造方法を提供することが出来て、
半導体チップの高集積化に伴って望まれる小型化ないし
リード端子数の増大化を可能にさせ、然も、該パッケー
ジの製造行程を単純化させる効果がある。(g) Effects of the Invention As explained above, the configuration according to the present invention provides a semiconductor device having a structure in which the interval between adjacent lead terminals of a pin grid array type ceramic package can be reduced, and its manufacture. We can provide a method,
This has the effect of making it possible to reduce the size or increase the number of lead terminals, which is desired as semiconductor chips become highly integrated, and to simplify the manufacturing process of the package.
第1図は従来のピングリッドアレイ型セラミックパッケ
ージを使用した半導体装置の一例の側面図(a)とその
構造を示す側断面図(bl tc+、第2図は本発明の
構造によるビングリッドアレイ型セラミックパッケージ
を使用した半導体装置の一実施例の側面図(a)とその
構造を示ず側断面図(bl tc+である。
図面において、1、laは絶縁基体、11〜13は絶縁
層、2a、2bは配線、3はスルーホール、4は端子座
、5.5aはリード端子、6は固定材、7は蓋、Aは半
導体チップ、Bはワイヤ、pl、plは端子ピッチをそ
れぞれ示す。
革/図
7
草Z図Figure 1 is a side view (a) of an example of a semiconductor device using a conventional pin grid array type ceramic package, and a side sectional view (bl tc+) showing its structure; Figure 2 is a side view (a) of an example of a semiconductor device using a conventional pin grid array type ceramic package; A side view (a) of an embodiment of a semiconductor device using a ceramic package and a side sectional view (bl tc+) not showing its structure. In the drawings, 1 and la are insulating substrates, 11 to 13 are insulating layers, and 2a , 2b is wiring, 3 is a through hole, 4 is a terminal seat, 5.5a is a lead terminal, 6 is a fixing material, 7 is a lid, A is a semiconductor chip, B is a wire, pl and pl are terminal pitches, respectively. Leather/Figure 7 Grass Z figure
Claims (2)
セラミックであって、該基体から外部に導出するリード
端子が該セラミック基体の焼成に耐えうる金属からなり
、その一部が該基体内に植え込まれていることを特徴と
する半導体装置。(1) The insulating base of the package on which the semiconductor chip is mounted is made of ceramic, and the lead terminals led out from the base are made of a metal that can withstand the firing of the ceramic base, and a part of the lead terminals are made of a metal that can withstand the firing of the ceramic base. A semiconductor device characterized by:
ク基体の焼成に先立ち、該基体の内部配線に繋げて該基
体に穿った孔に導電性物質を充填すると共にリード端子
の一部を挿入し、しかる後、該基体を該導電性物質と共
に焼成する工程を有することを特徴とする半導体装置の
製造方法。(2) Prior to firing the ceramic base of the pancage on which the semiconductor chip is mounted, a conductive material is filled into the hole bored in the base by connecting it to the internal wiring of the base, and a part of the lead terminal is inserted, and then a part of the lead terminal is inserted. . A method for manufacturing a semiconductor device, comprising the step of firing the base together with the conductive material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59042617A JPS60187046A (en) | 1984-03-06 | 1984-03-06 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59042617A JPS60187046A (en) | 1984-03-06 | 1984-03-06 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60187046A true JPS60187046A (en) | 1985-09-24 |
Family
ID=12640977
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59042617A Pending JPS60187046A (en) | 1984-03-06 | 1984-03-06 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60187046A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0289851U (en) * | 1988-12-28 | 1990-07-17 | ||
| US5067007A (en) * | 1988-06-13 | 1991-11-19 | Hitachi, Ltd. | Semiconductor device having leads for mounting to a surface of a printed circuit board |
| EP2516321B1 (en) * | 2010-12-02 | 2019-03-06 | Micro-Epsilon Messtechnik GmbH & Co. KG | Sensor comprising a preferably multilayered ceramic substrate and method for producing it |
-
1984
- 1984-03-06 JP JP59042617A patent/JPS60187046A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5067007A (en) * | 1988-06-13 | 1991-11-19 | Hitachi, Ltd. | Semiconductor device having leads for mounting to a surface of a printed circuit board |
| JPH0289851U (en) * | 1988-12-28 | 1990-07-17 | ||
| EP2516321B1 (en) * | 2010-12-02 | 2019-03-06 | Micro-Epsilon Messtechnik GmbH & Co. KG | Sensor comprising a preferably multilayered ceramic substrate and method for producing it |
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