JPS6019255A - Data memory method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a data storage method that reduces the complexity of memory address management when reading out stored data by reducing or rotating it.

Configuration of conventional example and its problems A data storage method that allows data rotated in 90 degree increments from a memory that can operate in parallel to be read and written in parallel by a predetermined bit regardless of the number of degrees of rotation, and a method for storing data. A data storage method that allows data reduced by a predetermined bit to be read and written in parallel from a memory that can operate in parallel when the reduction rate is specific, and furthermore, a data storage method that can operate in parallel when the reduction rate is specific. A data storage method has been proposed in which data that has been reduced by a predetermined bit and rotated by 90 degrees can be read and written in parallel from a memory that can operate in parallel, regardless of the reduction rate and rotation degree.

Figure 1 is a diagram showing an evening scene in the handling, with 432 bits in the horizontal direction (row direction), 576 bits in the vertical direction (column direction), and a total data amount of 432 x 575 bits.1) Data is input in the row direction. do. If a memory is to be constructed of memory elements (RAM) having a capacity of 1 bit x 64 words, four RAMs will be required. One memory is configured with one RAM so that each 4 bits can operate in parallel, making a total of 4 bits each.
Configure multiple independent memories. FIG. 2 is a diagram in which a memory circuit is constructed from four independent memories (lvH, M2, M3, M4).

First, a data storage method will be described in the case where data rotated in units of 90 degrees can be handled in parallel in 4-bit units regardless of the degree of rotation. In this case, each data is divided into 4 bits each in the row direction and column direction,
4×4=16 bit data is handled as a block unit. FIG. 3 is a diagram in which 432×576 bit data is divided into blocks of 4 bits each in the row direction and column direction, and is divided into 108 blocks in the row direction and 144 blocks in the column direction, for a total of 15,552 blocks. (i,+) indicates the block in the i-th row and j-th column. Furthermore, the 4×4 bit data in the block is numbered from 1 to 16 in the row direction VCJI starting from the first row and first column. FIG. 4 is a diagram showing 16-bit data in numbered blocks. When storing this numbered data, 4 bits are stored in parallel in each memory in FIG. 2 as shown in FIG. 6. With this storage method, data in the row direction and column direction within a block are stored in different memories, so that data rotated in units of 90 degrees can be read out in parallel 4 bits at a time.

Next, a data storage method will be described in the case where the data reduction rate, J-rate, is an exponential power of 2, and 4 bits can be handled in parallel regardless of the reduction rate. Assume that the maximum reduction rate of data is for columns. In this case, the 432-bit data in each row is divided into 27 blocks of 16 bits each, resulting in a total of 15,552 blocks. Furthermore, the data within each block is sequentially numbered from 1 to 16. Figure 2 is a diagram in which the data in each row is divided into blocks of 16 bits, and a diagram showing 16 bits of data in the numbered blocks. When storing this numbered data, 4 bits are stored in parallel in each memory in FIG. 2 as shown in FIG. 7. In this storage method, data obtained by sequentially dividing each 4 bits in each block, data obtained by sequentially dividing the results of sampling every 2 bits into 4 bits, and data resulting from sampling every 4 bits are stored in different memories. No reduction, reduction to V2, 'AVC reduced data to 4
Bits can be read out in parallel.

Next, a data storage method will be explained in the case where the data reduction rate is an exponential power of 2 and four bits can be handled in parallel regardless of the reduction rate and the number of rotations. Assuming that the maximum data reduction rate is specified, each data is divided into 16 bits in the row and column directions, and 16×16=256 bits of data are treated as a block unit. FIG. 8 is a diagram in which 432×576 pit data is divided into 16 bits each in the row direction and column direction, and is divided into 27 blocks in the row direction and 36 blocks in the column direction, for a total of 972 blocks. (113) indicates the block in the 1st row and jth column. Further, the 1'6 x 16 bit data in the block is numbered from 1 to 266 in order from the 1st row and 1st column in the row direction.

FIG. 9 is a diagram showing 256-bit data in numbered blocks. When storing this numbered data, 4 bits are stored in parallel in each memory in FIG. 2 as shown in FIG. 10. This storage method includes data that is sequentially divided into 4 bits in the row direction within the same block, data that is the result of sampling every 2 bits that is divided in 4 bits, data that is the result of sampling every 4 bits, and data that is the result of sampling every 4 bits, and the data that is the result of sampling every 4 bits, The data obtained by dividing the result of sampling every 2 bits into 4 bits each, and the data obtained by sampling every 4 bits are stored in different memories.
It is possible to rotate in units of 0 degrees and read data that is unreduced, reduced to a bar, or completely reduced to a column of 4 bits at a time.

The complexity of address management when reading data differs depending on the address in the memory at which each data is stored using the above storage method.
If data is simply stored in memory in the order in which it is input, address management for each memory becomes complicated when it is reduced and read out and when it is rotated and read out, and the circuit scale for address control increases.

OBJECTS OF THE INVENTION An object of the present invention is to provide a data storage method that facilitates address management of each memory when data is written in a memory, reduced and read out, and rotated and read out.

Structure of the Invention In order to achieve the above object, the present invention uses n bits (n≧1oq2 (total number of blocks)) of the address input to the memory to define the block, and the remaining m bits to determine the data position within the block. When writing data to memory, the value of n is made common for each memory within a block, and the address where the data converted to m is written to the memory is determined. To facilitate address management when reading by reducing the size and reading by rotating.

The amount of data to be explained in the embodiment is 432 x 576 bits as shown in Fig. 1, data is input in the row direction, and four independent memories (Ml, Ml, M2,
M3. M4) constitutes a memory circuit. Assume that the maximum reduction rate of the data is just, rotate in 90 degree units and do not reduce,
A case will be described in which data reduced to bars and pieces can be read out in parallel in 4-bit units.

FIG. 11 is a block diagram of one embodiment of the present invention. 1 to 4 are counters, each of which performs UP/DOWN operations.Counter 1 is 432x676 as shown in Figure 8.
Counter 2 is a counter that counts the columns of a block from 0 to 26 when the bit data is divided into 16 bits in the row and column directions.
Counter 3, which counts up to 6, counts rows within a block during row direction scanning, and counts columns within a block during column direction scanning. Counter from 0 to 16.

When scanning the block in the row direction, the 16 bits in the row direction within the block are divided into groups of 4 bits, and the groups are set from 0 to
This is a counter that counts up to 3.

6.6 is an address conversion circuit, and the address conversion circuit 6 determines the value of n bits that define a block based on the values of counters 1 and 2.The address conversion circuit 6 determines the value of counters 3 and 4, the rotation degree at the time of reading and reduction The ratio determines the value of m bits that define the data position within the block. Reference numeral 7 denotes a counter control circuit which determines the direction of counting 1 to 40, the arrangement of the counters, and the increment of the counters depending on whether writing or reading is performed, the number of rotations during reading, and the reduction rate.

8 is an S/P shift register that converts input data that is a serial signal into a 4-bit parallel signal; 91i is a shift register that takes in data from S/P shift register 8 and shifts the data cyclically; 1o is a shift register that converts input data that is a serial signal into a 4-bit parallel signal; 11 is a memory circuit composed of four independently operable memories shown in FIG.
2 is a shift register that takes in data read from the memory circuit 11 and circularly shifts the data; 13 is a data conversion circuit that converts the sequence of data from the shift register 12; and 14 is a column signal from the data conversion circuit 13. A P/S shift register takes in data and converts a serial signal, and 15 is a selector that switches the direction of data extraction from the P/S shift register 14.

Further, 16 and 17 are data control circuits, and the data control circuit 16 controls the values of the counters 3 and 4 and the shift amount of the shift register 9. The data control circuit 17 includes the counter 3,
4, the number of rotations at the time of readout and the reduction ratio of the shift register 12), the arrangement of data in the data conversion circuit 13, the direction of data extraction from the P/S shift register 14, and the selector 16. control switching.

In the present invention, among the address inputs to the memory, nun≧-1
oq 2 (total number of programs) The bit nodes are used as bits that define the program, and the remaining m bit nodes are used as the bits that determine the data position within the program. The number of data in a block is 16x16:256, and it is divided into four memories and stored, so m = lo as a bit that determines the data position in the block in the address input to the memory.
g264 requires 26 bits and 7 bits. The number of blocks is 27
x36=97'2 as the bit that defines the block n
”: l 0529γ2#10 Bi, 71. is required. Data is handled in parallel within the program, and as described above, the n Bi node is divided into blocks.
Since it is a node, the value n1 is given to each memory in common. m is professional, when reading by rotating or reducing within 7 degrees,
Each memory M1. M2゜M4 independently of its value m1. m2. m3. m
Give 4.

First, the data writing operation will be explained.

Data is input in the row direction, so the data is in the 12th column.
As shown in the figure, 4 bits are processed sequentially in the row direction. In FIG. 12, the circles indicate the order of the 4 bits 1, 1. data to be processed. Therefore, M h y of the counter
Control is performed so that the + direction is in the order of the counter control circuit 7 (◯→36). The address conversion circuit 6 shows the value of the counter 1 as 81 and the converted value in the counter diagram. If the value of counter 3 is 83 and the value of counter 4 is a4, the address conversion circuit 6 is a binary representation of 4・a 3 +84.
Create the value of ml-m2-m3-m4 of bit. The data control circuit 16 creates the amount by which the shift register 9 is shifted based on the values of the counters 3 and 4 so that the data shown in FIG. 10 is stored in each memory.

The f-direction is 5-m0d4 (a4+m0d4a3).

FIG. 16 shows the values and shift amounts of m1 to m4.

Counters 1 to 4 arranged as shown in FIG. 13 count each time the input data is converted by the S/P shift register 8 into parallel data of 4 bits/nodes. The data converted into parallel data of 4 bits each in the S/P shift register 8 is cyclically shifted to the right in response to the shift amount command from the data control circuit 16 in the shift register 9 to arrange the data. Convert and send data to latch 10. The data from the latch 10 is transferred to the new memory circuit 1104 memories (Ml, M2, M3, M4) by the value n1.6 from the address conversion circuit 5.6. Write to addresses corresponding to m1 to m4.

If n is the upper 10 bits of the memory address input and m is stored as the lower 6 bits of the memory address input, each block in FIG. 8 corresponds to each address in the memory shown in FIG. 16, The data within the block is stored at each address in each memory as shown in FIG.

FIG. 18 is a diagram showing addresses where data is stored.

In FIG. 18, (iIJ) indicates a block, and I indicates data within the block.

Next, the data read operation will be explained.

Figure 19 is a diagram showing the order in which data is read and processed.
indicates the order of data to be processed in units of 4 bits.

FIG. 20 is a diagram showing the arrangement of counters and counting directions. In Figures 19 and 20, (-) indicates that! Ma,
(b) rotated 90° to the left, (C) rotated 180°, (d)
is rotated 90 degrees to the right, (e) is reduced in diameter, (f) is 900 turns left and reduced in diameter, (q) is reduced to 1800 turns, (h) is 900 turns to the right - reduced in m, (i) is A Reduced, (i) left 9
0° rotation/Vi reduction, (k) 1800 rotation/dead reduction,
(1) shows the case of 900 rotations to the right and % reduction. If you want to reduce and read the data in odd rows and columns,
When reading by reducing bit by bit to %, 41+1 rows.
Assume that 4 pits of data in 41+1 columns are to be processed. In the case of over-reduction, counters 3 and 4 count by 2, and in the case of % reduction, the value of counter 4 is fixed to 0, and counter 3 counts by 4.

The address conversion circuit 6 converts nl into the value shown in FIG. 14 in accordance with the values of the counters 1 and 2 in the same way as when writing. The address conversion circuit 6 converts m11m22m37m4 according to the value of count 3゜4, the rotation degree and reduction rate at the time of reading.
to each memory.

When rotating oo and 180' without reduction, m1 to m4 are the first
This is the same value as when writing shown in FIG. When performing 90Q rotation to the left and right without reduction, the values m1 to m4 shown in FIG. 21 are created and given to each memory. 00 and 180 with dedicated reduction
Figure 22 (a) at 0 rotation, left and right 900 when reduced
When rotating, the values m1 to m4 shown in FIG. 22 are created and given to each memory. Create the values of m1 to m4 shown in Figure 23 (a) for 00 and 1000 rotations with % reduction, and Figure 23 (b) when 90 degrees left and right rotation with % reduction,
Give each memory. In FIGS. 21 to 23, m1 to m4 are expressed as decimal values.

Counters 1 to 4 arranged as shown in FIG. 20 count each time data is read out in parallel from the memory circuit 11 by 4 bits. The values counted by counters 1 to 4 are the same as when writing. The four memos I) (Ml, M2°M3.M4) of the memory circuit 11 are the values n1.M4 from the address conversion circuits 6, 6. Read data at addresses corresponding to m1 to m4. The shift register 12 performs a cyclic shift to the left in response to a shift amount command from the data control circuit 17 to convert the arrangement. The shift amount is the same as that for writing, and is the same as the above-mentioned S ”” mOd 4 (cL4 +rl
ll O, d 4 a 3 ). The data conversion circuit 13 does not rearrange the data when there is no reduction and the column line /'' is instructed by the data control circuit 17, and exchanges the second and third data from the shift register 12 when μ reduction is performed. The data is taken out from the P/S shift register 14 and selector 16 according to the commands of the data control circuit 17 (for poo and 90° rotation to the left, data shifted to the left is used, and for 1800° and 900° rotation to the right, data is shifted to the left). Extract the data shifted to the right.

Effects of the Invention As described above, the present invention provides the following effects.

(1) Since n bits of the address input to each memory are handled as common bits, it becomes easier to manage addresses during data reduction and rotation, thereby reducing the circuit scale around address control.

(a) This is useful because it makes it easier to manage memory addresses.

[Brief explanation of drawings]

Figure 1 shows the amount of data to be handled, Figure 2 shows the configuration of four independent memory circuits, Figure 3 shows data divided into 4 bits each in the row and column directions, and Figure 2 shows the configuration of four independent memory circuits. 4
The figure shows 16-bit data in the numbered blocks, and Figure 5 shows the 4-bit data stored in each memory in Figure 2.
Figure 6 is a diagram showing the data in the figure, and the data in each row is 16 bits at a time. Figure 7 shows the data in Figure 6 stored in each memory in Figure 2.
Figure 8 shows the data divided into 16 bits in the row and column directions, Figure 9 shows the 266-bit data in the numbered blocks, and Figure 10 shows the 266-bit data in the numbered blocks.
A diagram showing the data of FIG. 9 stored in each memory in the figure, FIG. 11 is a block diagram of a device embodying the storage method of one embodiment of the present invention, and FIG. 12 is a diagram showing the data processed when writing from the row direction. FIG. 13 is a diagram showing the counter configuration at the time of writing, FIG. 14 is a diagram showing the value of n from the address conversion circuit 6, and FIG. 16 is the address at the time of writing. A diagram showing the values of m1 to m4 from the conversion circuit 6, FIG. 16 is a diagram showing the memory address to which the block corresponds, and FIG. 17 is a diagram showing the memory address to which the data in the block corresponds. ml given to each memory when ~
The values of m4 are shown in Fig. 22 (,) when A is reduced at 0° and 1800 rotations, Fig. 22 (b) is when rod reduction is made at 900 rotations left and right, Fig. 23 (a) is ) is the ml given to each memory when V41Ad is small at 0° and 1800 rotations, and Figure 23 (b) is % reduction and 900 rotations left and right.
It is a figure showing the value of 4. 1 to 4... Counter, 5, 6... Address conversion circuit, 7... Counter control circuit, 8...
...S/P shift register, 9...Shift register, 1o...Latch, 11...
・Memory circuit, 12...Shift register, 13.
...Data conversion circuit, 14...P/S shift register, 15...Selector, 16.17.
...Data control circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person
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Claims (1)

[Claims] Data is divided into blocks of NxM (N, M is an integer greater than or equal to 2) bits, and the data in each block is decomposed into N memories that can operate in parallel in order of N bits. When writing, or data is written in NxM in row direction and column direction respectively.
(N is an integer greater than or equal to 2, and 2M is an integer greater than or equal to 1) Divide into bits, treat (NxM) x (NxM) bits of data as a block unit, and sequentially divide the data in each block by N bits from the column or row direction. When dividing and writing into N memories that can operate in parallel, n [, n≧ll0q2 (total number of blocks)] bits of the address input to the memory are used as bits that define a block, and the remaining m bits are used as blocks. a bit that determines a data position in the memory, the value of the n bits input to the N memories that can operate in parallel is set in common, and the value of the m bits input to the N memories is set to a predetermined value, respectively. A data storage method characterized by writing and reading data in N bits in parallel.