JPS60201441A - Microprogram control device - Google Patents

Abstract

PURPOSE:To shorten a block loading time by loading the next block by keeping pace with the execution of a micro-instruction word of the present block at the time point when a block to be executed in the next time is known logicaly in a block which is being executed. CONSTITUTION:In order to confirm a fact that a micro-instruction word to be executed after several steps of a micro-instruction which is being executed exists in a control memory 12, a micro-instruction word for an advance-taking instruction is read out in a micro-instruction register 13. Subsequently, it is decoded by a decoding circuit 14, and inputted to an advance-taking micro-instruction address generating circuit 15. With regard to whether a block containing an advance-taking micro-instruction word is stored in the control memory 12 or not, an address array 16 and a block number of an advance-taking micro-instruction address register 19 are compared by a comparing circuit 17'. Unless it is stored, a block is loaded to the control memory 12 from a secondary storage part 11 by keeping pace with an instruction which is being executed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a microprogram control device, and particularly relates to block loading of a horizontal microprogram control device employing a cache method in a microprogram control device in a data processing device. It is.

(Prior Art) Conventionally, a horizontal microprogram control device employing a cache method has determined whether a block containing a microinstruction word exists each time a microinstruction word is executed. Therefore, this horizontal microprogram controller has the disadvantage that if a block does not exist, it is necessary to load the block at that point, and the execution of the microprogram must be interrupted during this time.

(Object of the Invention) It is an object of the present invention to eliminate such drawbacks in conventional microprogram control devices, and to use the instructions of a microinstruction word to By checking the existence of the next block in the control memory and starting the block load when it does not exist, and loading the next block in parallel with the execution of the microinstruction word of the current block, the microinstruction of the next block is actually executed. To provide an apparatus in which the block loading is completed or the block loading time is shortened as much as possible by the time an attempt is made to start the block loading. a control memory consisting of a plurality of compartments capable of storing information, an address array having a plurality of entries for holding management information of the control memory and the cheater block of the secondary primary memory, and a microinstruction word to be executed. means for testing whether a block exists in the control memory and loading the block from a secondary storage unit into the control memory if the block does not exist; a microinstruction register for holding the microinstruction; In a cache-type horizontal microprogram control device that executes microinstructions in the instruction register, the address of the microinstruction word is used to specify a prefetch instruction corresponding to an instruction that does not instruct a specific field in the microinstruction word. a prefetch microinstruction address generation circuit that generates a prefetch address based on output signals of the decode circuit and the microinstruction register; and a prefetch microinstruction address register that holds the prefetch microinstruction; means for indexing the address array with the contents of the prefetch microinstruction address register in parallel with execution of the microinstruction; and determining whether a block containing the prefetch microinstruction address exists in control memory as a result of the indexing. A microprogram control device is obtained, comprising means and means for loading the non-existing block into a control memory in response to execution of the microinstruction if the result of the determination is non-existent.

(Example) Next, an example of the present invention will be described in detail with reference to the drawings.

The drawing shows an embodiment of the invention. In the figure, the present embodiment includes a control memory 12 consisting of a plurality of compartments capable of storing a plurality of microinstructions, a secondary storage section 11 storing microinstructions, and the control memory 12.
and an address array 16 that holds management information for data blocks in the secondary storage unit 11 and has a plurality of entries, and a block that includes a microinstruction word to be executed is tested to see if it exists in the control memory 12. If not, the control memo! is stored in the secondary storage unit 11. This is a cache-type horizontal microprogram control device that has a microinstruction register 13 that holds the microinstructions as well as means for loading blocks into J12, and executes the microinstructions in the microinstruction register. A decoding circuit 14 decodes a specific instruction including the address of a microinstruction word in order to give a prefetching instruction corresponding to an instruction that does not instruct an operation to a specific field, and a prefetching address is generated from the output signals of the decoding circuit and the microinstruction register. a prefetch microinstruction address generation circuit 15 for storing the prefetch microinstruction address; a prefetch microinstruction address register 19 for holding the prefetching microinstruction; and a prefetching microinstruction address register 19 for holding the prefetching microinstruction; The block containing the prefetched microinstruction address as a result of said index is stored in the control memory'.
J12, and means io for loading the non-existing block into a control memory in parallel with the execution of the microinstruction if the result of the judgment is that the block does not exist.

The control memory 12 is a secondary storage unit 1 that stores micro life alloys.
The microinstruction register 13 is a memory that holds a part of the microinstructions extracted from the control memory 12, and the microinstruction register 13 is a register that holds the microinstructions newly issued from the control memory 12, including an operation instruction section and a branch address section. Decode circuit 14
decodes a specific instruction in a specific field in the microinstruction register 13 that contains the address of a microinstruction word for not instructing an operation, that is, instructing a prefetch to replace a NOP instruction. It is supplied to the instruction address generation circuit 15 and the control circuit. The prefetch microinstruction address generation circuit 15 generates a prefetch address of a microinstruction to be executed several steps after the currently executed microinstruction from the output signal of the decode circuit M14 and the output signal of the microinstruction register 13, and generates a prefetch address of a microinstruction to be executed several steps after the currently executed microinstruction. Supply to 19. The address array 16 holds management information for data blocks in the secondary storage section 11 and control memory 12 and has a plurality of entries, and the micro 6 instruction address register 18 is used to execute execution from the microinstruction word currently being executed to the next step. It holds the address of the microinstruction to be executed. The indexing means 16 is constituted by a comparison circuit, and is a circuit for indexing whether or not a microinstruction to be executed in the next step currently being executed in the control memory exists in the control memory 12. The output signals of the instruction address register 18 are compared and the result is sent to the control circuit 1.
Supply to 0. Prefetch microinstruction address register 1
A register 9 holds the prefetch microinstruction address generated by the prefetch microinstruction address generation circuit 15. The determining means 17' is composed of a comparison circuit, and is a circuit for indexing whether or not a block containing a microinstruction to be executed several steps after the microinstruction being executed exists in the control memory 12. The output signal is compared with the output signal of the prefetch microinstruction address register 19, and the result is supplied to the control circuit MIOK. The control surface #810 of the present microprogram control device uses the above judgment result to store the block in the secondary storage in parallel with the execution of the microinstruction if the block containing the microinstruction does not exist in the control memory 12. It is used to control the loading from to the control memory.

In this embodiment, the control lines from the control circuit 10 to each block will be omitted and only the information lines will be described.

Next, the operation of this embodiment will be explained in detail.

First, a case will be described in which microinstruction prefetching is not performed. When the micro-instruction word to be executed is extracted from the control memory 12 and stored in the micro-instruction register 13, the output of the micro-instruction register 13 is sent to the control plane 1i! to instruct the micro-instruction to operate according to 9-. 1IOK is input.

In the control circuit IO, the operation instruction part of the microinstruction word controls various operations of the microprogram control device, while the branch address part of the microinstruction word indicates the address of the microinstruction word to be executed in the next step currently being executed. is generated and stored in the microinstruction address register 18.

A comparison circuit checks whether the desired microinstruction is stored in the control memory 12 in order to store the microinstruction to be executed in the next step from the control memory 12 into the microinstruction register 13 after the currently executed microinstruction has finished. 17
Then, the block numbers in the address array 16 and the microinstruction address register 18 are compared, and if a match is found, the next microinstruction to be executed is in the control memory 1.
This means that the microinstruction word exists in the microinstruction register 13 from the control memory 12 and is executed as is.

However, if a match cannot be found as a result of comparison, comparison times -l〇
- The output of the path 17 is input to the control circuit 10, and execution of the microinstruction is inhibited.

When the control circuit 10 receives the signal that does not match, it creates a secondary storage address from the block address of the microinstruction address register 18, and transfers the block load from the secondary storage section l to the control memory 12 so that the reloaded block is controlled. The block number of the block is stored in the memory 12 and also held in the address array 16. When the storage is completed, the control circuit 10 initiates restart of the microprogram.

Next, the case where microinstruction prefetching is performed will be explained. 111! indicates that a microinstruction word to be executed several steps after the microinstruction being executed exists in the control memory 12! In order to recognize this, a microinstruction word that instructs prefetching corresponding to a NOP instruction is stored in the microinstruction register 13.
When issued, the specific instruction is decoded by the decoding circuit 14 and its output is sent to the preemption microinstruction address generation circuit 1.
5 is input.

The optical range microinstruction address generation circuit 15 generates the address of a microinstruction to be executed several steps after the currently executed microinstruction based on the address of the microinstruction currently being executed and the output of the decoding circuit 14, and uses the address of the microinstruction to be executed several steps after the currently executed microinstruction. Inputs instruction address register ILK. The block containing the prefetch microinstruction word is a control memo')12
At the comparison step Ml7', the block numbers of the address array 16 and the prefetch microinstruction address register 19 are compared, and if they match, it is determined that the desired microinstruction word exists in the control memo IJ12. This means that the microinstruction several steps later is also executed as is.

However, if a match cannot be found as a result of the comparison in the comparison circuit 17', the output of the comparison circuit 17' is manually inputted to the control circuit 181O.
The block containing the prefetch microinstruction is block-loaded from the secondary storage unit 11 to the control memory 12 in parallel with the currently executing Mic I:I instruction without inhibiting the microinstruction currently being executed. The block number of the block is also held.

When the microinstruction several steps after the microinstruction being executed is about to be executed, the block exists in the control memory 12 or is being prefetched, so there is no need to start block p-do from that point. The execution time of microprograms is reduced.

Also, depending on the sequence, there is a risk that the bit rate of the control memory 12 will decrease due to prefetching, but such a case can be resolved by implementing effective block allocation of the secondary storage section 11.

(Effects of the Invention) As explained above, the present invention converts the control memory into a cache λ and enables block loading by making it possible to prefetch a block containing microinstructions that are collected several steps after the microinstruction being executed. This makes it possible to ignore or shorten the time required, which has the effect of improving microprogram execution time.

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[Brief explanation of the drawing]

The drawing is a block diagram showing one embodiment of the present invention. lO... Control circuit, 12... Control memory, 13... Micro instruction register, 14...
... Decoding circuit, 15 ... Preemption microinstruction address generation circuit, 16 ... Address array, 17, 17' ... Comparison circuit, 18 ...
...Microinstruction address register, 19...
- Prefetch microinstruction address register. 14-

Claims (1)

[Claims] A control memory consisting of a plurality of compartments capable of storing a plurality of microinstruction words, and an address array that holds management information of data blocks in the control memory and a secondary storage section and has a plurality of entries. , means for testing whether a block containing a microinstruction to be executed exists in the control memory, and if not, loading the block from a secondary storage section into the control memory; In a cache-type horizontal microprogram control device that has a microinstruction register and executes microinstructions in the microinstruction register, prefetching corresponds to an instruction that does not instruct an operation to a specific field in the microinstruction word. a decoding circuit that decodes a specific instruction containing a 1-address of a microinstruction word for issuing an instruction; a prefetch microinstruction address generating circuit that generates a prefetch address based on the output signal of the decoding circuit and the microinstruction register; a prefetch microinstruction address register for holding a microinstruction; Prl means for indexing the address array with the contents of the prefetch microinstruction address register in parallel with execution of the microinstruction; and a prefetch microinstruction address as a result of the indexing. means for determining whether or not a block exists in the control memory; and, if the result of the determination is that the block does not exist, means for loading the non-existing block into the control memory in parallel with execution of the microinstruction. A horizontal microprogram control device with special features.