JPS60207933A - Data processor - Google Patents

Abstract

PURPOSE:To execute the decoding of an instruction at a high speed by processing two operands simultaneously when a non-register designator appears following an operand designator for specifying a register. CONSTITUTION:A register specification mode detecting means 517 checks whether the leading operand designator on a signal line 329 is in a register specification mode or not. If said operand designator is in the register specification mode, data on the signal line 329 are outputted to a signal line 21A as they are through an operand designator operating means 516. In case of register specification, the 2nd operand designator and the 1st operand designator are decoded by an operand specification decoder 505 and a register specification mode decoder 506 respectively and simultaneously.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a pipeline control data processing device that handles variable length instructions in which an oherrand specifier is given independently from a code section specifying an operation, and in particular, The present invention relates to a data processing device that processes two operands simultaneously by manipulating the order of operand specifiers that appear in the order of register designation and non-register designation, when a sequence of operand specifiers is detected.

[Background of the invention]

Until now, the instruction system with variable-length operand specifiers was
Although this is well known, FIG. 1 shows one example thereof.

According to this JL, Figures (A) and (B) respectively show the format of the operand specifier when the operand is given as literal data. 5h shown in figure (A)
ort Literal format, and in the case of literal data with a length of 6 bits or more, the format is as shown in Figure 1 (B).
The format is Long Li serial as shown in the figure below.

In addition, Figure 1 (C) shows the format of the operand specifier in register specification mode, where the register at the address specified in the field II Rn'' becomes the operand. It shows the format of the operand specifier at the time, and consists of a register at the address specified by the "Rn" field, a "Disp len" part that shows the displacement length, and a displacement part "D i sp". .

Furthermore, FIG. 1(E) shows the format of the operand specifier in program counter relative mode.
gp len” part and 110 i 811 parts.

Finally, FIG. 1(F) shows the format of the operand specifier in the Absolc+Le mode, where the field indicated by 'Abso' directly indicates the memory address where the operand is located.

The format of the operand specifier shown in FIG. 1 is only one example of the various addressing modes, and it goes without saying that there are various other formats of operand specifiers, but these are not necessary for understanding the present invention. Therefore, it will be omitted.

In the instruction system described above, even if the opcode is the same, the length of the instruction word will generally vary, and although the first field of the instruction word is fixed as the opcode, the other parts can have various meanings. Therefore, the meaning of the fields in the instruction word is not uniquely determined, and the operand specifier included in the instruction word changes its length depending on the addressing mode, so even if the operation code is the same, the instruction word The length of can take various values. Therefore.

If an instruction decode unit that handles such an instruction system were to take in one instruction word at a time and decode that instruction, the scale of the hardware would be enormous and it would be complicated. The disadvantage is that it requires some control.

On the other hand, as an instruction decoding means, a method can be considered in which a specific unit of length is determined and the instruction word is taken in and decoded by one or more unit lengths, but 8-bit ( If the basic unit is 1 byte), the instruction length for a basic instruction is 3 to 7 bytes.1For example, if the decoding of the instruction word is to proceed in synchronization with the machine cycle, the number of bytes of the instruction word will be required to decode one instruction. However, the decoding of instructions becomes slower, which has a big negative side in terms of speeding up processing.

In this way, in the data processing device a having the above-mentioned instruction system, it is important to perform pipeline processing efficiently by speeding up the instruction decoding process. The reality is that it cannot be done.

By the way, one method for performing instruction decoding processing at high speed is described in Japanese Patent Laid-Open No. 161943/1983. According to this, especially when the final operand specifier is a register specification, the instruction It has been shown that decoding can be performed at high speed. However, various addressing modes are used in actual programs, and according to the frequency of use 1,
There is also a high probability that an operand specifier for an addressing mode other than register specification will appear following an operand specifier for register specification.

However, conventional data processing devices have not been able to speed up instruction decoding processing for the above-mentioned combinations of operand specifiers.

[Purpose of the invention]

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a data processing device that can perform instruction decoding at high speed when a register-specifying operand specifier is followed by a non-register-specifying operand specifier.

[Summary of the invention]

For this purpose, the present invention is configured such that when it is detected that an operand not specifying a register appears following an operand specifier specifying a register, time processing between two operands is performed.

[Embodiments of the invention]

The present invention will be explained below with reference to FIGS. 2 to 5.

First, the configuration of a data processing device to which the present invention is applicable will be described. FIG. 2 shows an example of the configuration. The relationship between the abbreviations and official names in FIG. 2 is as shown in Table 1 below.

Table 1 In this Figure 2, the main memory bag [(MM) 301 is
Main memory control unit (MCU) 3.0 stores the variable length instructions mentioned above and the operands handled by these instructions.
High-speed buffer memory (BM,) 3 under control from 2
Data is exchanged with 03 and (BMQ) 304.

Address buses 320, 323, 340, 342 and data buses 321, 324, 34L 343 are for transmitting and receiving data.

Now, to explain the remaining parts, the instruction fetch unit (IFtJ) 305 sends the address of the instruction to the BM 303 via the signal line 327, so that the instruction word is issued in advance. IFU3
The instruction taken into 05 is sent to the instruction decode unit (DU).
309 via a signal line 329 in units of opcodes and operand specifiers, and are decoded.

In the atray calculation unit (AU) 310, the signal line 336
The effective address of the operand is calculated according to the addressing mode decoded by the DU 309 from the DU 309, and the result is given to the operand offset unit (OFU) 311 via a signal line 337. 01
``In tJ311, the address of the operand from ΔU310 is sent to 13M and 304 via the signal line \330, and the operand is fetched in advance.BM.

If 304 has data corresponding to the address from OF[3]1, it immediately passes the f-t to 0FU311 via the signal line 331, but if data corresponding to the corresponding address does not exist, MCU3O,2 via MM301
is accessed, data corresponding to the address is read out, and the data is passed to 0FU31+.

The execution unit (EU) 312 receives the operand from the 0FU 311 via the signal line 338 and executes the instruction.

Note that each unit operates almost independently and performs vibe line processing between operands. Also, Figure 2 Neutral No. 41
0 indicates a data bus.

The data processing devices to which the present invention is applicable are as described above, but more specifically, the present invention is applied to an instruction decoding unit.

FIG. 3 shows a concrete construction of an example of an instruction decoding unit directly related to the present invention. The relationship between the abbreviations and official names in FIG. 3 is as shown in FIG. 2.

Table 2 Without going into details here, the μ program address generation circuit (EC3AG) 501 inputs the micro program address IOB of the previous application executed by EtJ312.
It is generated by the operation code given from the FU 305 via the No. 1 tfA329.In the mepeland information memory (+) O3) 503, the signal a3
The operand specifier decoder (O3-DEC:) 505 stores information regarding the operand in the opcode given from 29 through the selector (SET, ) 502, and decodes the operand 1-specifier in the signal a21A. There is.

Register specification mode detection means (RDD)',)
] 7 detects whether the operand specifier to be decoded next is in the register specification mode, and the detection result is (08-A through the a-segment lines 17Δ and 18A, respectively
LIG516. Sent to ACIG504. Means for manipulating the order of operand specifiers (O3-AL I G)
516, when the register specification mode operand specifier detection signal is input from the RDD 517 via the signal line 17Δ, the data on the signal line 329 (the sequence of opcode and operand specifier to be decoded next) is specified as a register. The signal a2 is shifted (deleted) by the number of bits (bytes) occupied by the mode operand specifier.
It is designed to output at 1A. At the same time, set the register specification mode operand specifier (H single line 20
A sends a signal indicating that the above-mentioned processing has been carried out (the signal output to each branch line 19A is roaring.R'D
When register designation mode detection No. 44 is not output from D 517, 03-ALI 0516 does not perform any special operation and the contents of signal line 329 are output as they are to signal line 2LA. In the control data generation circuit (ACIG) 504, DC503,08-DEC505 and RDD51
Address calculation unit, (AtJ) with information from 7
At step 310, control data 336 for calculating addresses of operands is generated. The register detection mode decoder (RD-DEC) 506 detects whether the data from the selector (SEL) 515 is an operand specifier for a register specification, and if it is a register specification, the address of the register is (i Branch line 12
It is set in a register in the AU 301 via B.

Decode bit (byte) number calculation means (DBNC) 50
7 is 08-DEC505 and RD-DEC50G
The number of bits to be decoded in that cycle is calculated from the signal from.

Data aligner (D-AL IG) 508 is 08
- If the O8 to be decoded by the DEC 505 includes literal data, displacement, or absolute address, it is extracted and rearranged.

A control circuit (D-CONT) 509 receives the signal 12A from the control circuit of the IFU 305 and controls the overall operation of the DtJ 309.

A register (DP) 510 indicates the start address of data to be decoded in that cycle.

A selector (SF, L) 511 selects data to be set in the DP 510.

The incrementer (INC) 512 increments the content 1]Δ of the DP 510 by the number of bits of the instruction decoded in that cycle.

Means for calculating the number of bits (bytes) required for decoding (NL3
NG) 513 receives No. 43 from 03-DEC 505, reads it from the instruction buffer in IFU 305, and calculates the number of bits (bytes) required for decoding in that cycle. The program counter value calculation means for address calculation (TPCC) 514 calculates the value of the program counter necessary for performing address calculation relative to the program counter of the OS to be decoded.

Next, the instruction processing sequence in this embodiment will be explained using a basic instruction as an example.

As mentioned above, the IFU 305 is connected to the buffer memory BM, 3.
The prefetched instructions are sent to the DU 309 via the signal line 329. In this case, the signal line 329 has a data bit width sufficient to include at least one set of operand specifier and opcode. When the head of the signal line 329 is an opcode, the register designation mode detection means (RDD) 517 checks whether the first operand specifier following it is a register designation. If the register is not specified, the data on the signal line 329 is directly output to the signal line 21Δ via the OS-ΔL I G516, but in this case, the 5EL515
1A is selected. Also, if it is a register specifier, 08-ALIG516 is the signal line 329
The above data is shifted by the number of bits of the first operand and output to the signal line 21A, and at the same time, the first operand specifier is output to the (n) line 20A. At the same time, signal line 2 is connected to 5EL515.
No. m for selecting data on 0A is output via signal line +9A. Therefore, if the first operand is in register specification mode, the second operand specifier is 05-DE
C505, and the first operand specifier is RL) -
This means that they are simultaneously decoded by the DEC 506.

By the way, the opcode and the operand specifier that follows it are not always output to the signal line 329;
If there are a large number of operands, it may be possible that no opcode is included and only an operand specifier is included. In such a case, the RDD 517 checks whether the first operand specifier on the signal a329 is in register specification P mode.
O3ALI051G and 5EL51 for the results
5 performs the same operation as in the above case.

FIGS. 4 and 5 respectively show the flow of instructions and the accompanying instruction processing process. According to this, although FIG. 4 shows the stage flow of a two-operand instruction, both operand specifiers are not in register specification mode.

Therefore, in this case, two operands are not processed simultaneously, and two machine cycles are required to decode the two operand specifiers. Further, FIG. 5 shows a case where the first operand specifier is a register specifying mode and the second operand specifier is not a register specifying mode. In such a case, according to the present invention, the first operand specifier and the second operand specifier will be decoded simultaneously in the DU 309. Conventionally, it took two machine cycles to decode an instruction even in such a case, but according to the present invention, it only takes one machine cycle.

〔Effect of the invention〕

As explained above, in the case of the present invention, decoding of operand specifiers that previously required two machine cycles for combinations of operand specifiers such as register specification - non-register specification, which occur relatively frequently, now takes two machine cycles. By decoding the operand specifiers simultaneously, the decoding can be completed in one machine cycle, and therefore the instruction processing speed of a data processing device that performs pipeline control is improved.

[Brief explanation of drawings]

Figures 1 (A) to (F) are diagrams showing the format of instructions with variable-length operand specifiers, and Figure 2 shows the block configuration of an example of a data processing device to which the present invention is applicable. 3 is a diagram showing a specific configuration of an example of the instruction decoding unit r according to the present invention in its configuration, and FIGS. FIG. 301... Main memory device, 302... Main memory control unit, 303, 304... High speed buffer memory, 30
5... Instruction fetch unit, 309... Instruction decode unit, 310... Address calculation unit, 3
11... Operand fetch unit, 312...
Execution unit, 505...operand specifier decoder,
506...Register specification mode decoder, 517...
・Register specification mode detection means, 516...operan number /I! 1 (A) 14-3 → -C −−− No. ! 5th ■−〇Dtj Doooo■ 8μ H−−→ ■ OFσ ←−−8 Suzu −−−−+

Claims (1)

[Claims] 1. A main memory that handles variable-length instructions in which an operand specifier that specifies the addressing mode of an operand is given independently from a code section that specifies an operation, and that stores the variable-length instructions or data. , an instruction successive output means for reading instructions from the main memory, an instruction decoding means for decoding the instructions from the instruction successive output means, an address calculation means for calculating an address of an operand based on information from the instruction decoding means; Data consisting of an operand manipulation means that successively writes and writes data to an operand in the main memory indicated by an address from the address calculation means, and an execution unit that performs an operation according to the operation instruction received from the instruction decoding means. In the processing device, in the instruction decoding means, an operand specifier from the instruction reading means sets a register in the execution unit to the first register.
means for detecting a specific operand specifier that specifies a register other than a register in an execution unit as a second operand following an operand specifier specified as an operand; If a specific operand specifier sequence is detected, the first . means for respectively extracting second operand specifiers, means for decoding the extracted first and second operand specifiers from the means in the same cycle, and specific decoding processing by each of the above means. 1. A data processing device comprising: means for notifying an address calculation means that the calculation is being performed.