JPS6022258A - Data processor - Google Patents

Abstract

PURPOSE:To obtain a data processor with a simple constitution operated by a cache memory by providing a request control means and a switching control means to form a sub-model of a high speed data processor adopting two cache memories. CONSTITUTION:An instruction word is stored in an instruction register 1 of a data processor to designate one entry of an index register 2. An output of the register 2, address shift and the base address of a base register 3 are added by an operand address adder 5 to produce a virtual operand address. A relative address of an instruction counter 4 and a base address are added by an instruction address adder 6 to produce a virtual address. The virtual operand address and the virtual address are fed to the cache memories 11, 16 via address switching circuit 7, 12 and address conversion buffers 9, 14 or the like. Then a high speed data processor adopting the 2 cache memories is formed as a sub-model to simplify the constitution of the data processor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Description of the technical field to which the invention pertains] The present invention relates to a data processing device having two cache memories.

[Description of prior art]

In a data processing device with a built-in program, instruction words and operands are stored in the main memory, so the access time to the main memory has a large effect on performance. Therefore, a method of reducing main memory access time equivalently by providing a high-speed, large-capacity cache memory is also widely used. In recent years, a method has been proposed in which a cache memory for cached instructions for operands is provided separately to avoid contention in accessing the cache memory.

Although this method is extremely effective, it requires the provision of two cache memories and involves an increase in the amount of hardware. In addition, in a data processing device that employs a virtual address system, an address translation buffer TLB (TLANSLATION LOOKAS) is used to convert virtual addresses into real addresses.
This is a common method of indexing the cache memory using the real address 2 obtained by the IDE BUFFER.

If the virtual address method is applied to the two separate cache memories described above, it is necessary to provide a TLB for each cache memory, and the amount of hardware increases in this respect as well.

Although such an increase in the amount of metal is essential from the viewpoint of improving performance, it has the disadvantage of increasing failure rate and decreasing operating rate.

In order to solve this problem, there is a method of isolating the failed cache memory and replacing it with the remaining cache memory, but operand fetch requests and instruction fetch requests concentrate on one cache memory and cause contention. Occur. For example, it is based on sending out a selection in a two-cache memory as shown in FIG. A control method is conceivable in which request sending control with priority on operand retrieval is applied when one cache memory is in operation. As an example of pipeline operation using this method, instruction supply is 2 instructions/1 request.

FIG. 6 shows a case where the instruction buffer capacity is 4 instructions.

In FIG. 6, since the sending priority of an instruction fetch request is lower than that of an operand fetch request, the instruction fetch request is made to wait until the instruction buffer becomes empty and instruction supply is interrupted, and immediately after the instruction supply is interrupted, the instruction fetch request is sent to the instruction buffer. Make as many requests as you can. Instruction retrieval is also processed by the Tsukuibline until the instruction word arrives.

The execution cycle is 3 idle cycles! 11. A request to the cache memory also causes one cycle to be idle, which has the drawback of severely degrading performance.

On the other hand, in the data processing equipment market, high-speed models alone lack versatility, and
A machine family including low speed models is required. Conventionally,
Because the medium-speed model was designed completely separately from the high-speed model, it had the disadvantage of requiring a lot of development cost and development time.

[Detailed description of the invention]

An object of the present invention is to switch between addresses to be transferred to two cache memories and between output data according to cache-memory connection instruction information, thereby changing the operation from using two cache memories to only one cache. This makes it possible to degenerate into operation.

The objective is to improve operability against cache failures.

Another object of the present invention is to perform low-cost medium-speed data processing in a high-speed data processing apparatus employing two cache memories, which operates with only one remaining cache memory even when one cache memory is deleted. An object of the present invention is to provide a data processing device having a device as a submodel.

Another object of the present invention is to provide a data processing apparatus in which the above-described performance degradation when only one cache memory is operated is further reduced by optimizing cache request sending control.

[Structure of the invention]

According to the invention.

In a data processing device having a cache memory.

Each includes a pair of a data array that stores data retrieved from the main storage means, and an address array that stores a correspondence between a storage address in the data array regarding the data and a storage address in the main storage means, each of which has a different address. first and second cache memories capable of responding to.

operand fetching control means for sending an operand fetching request in response to an instruction register of the data processing device;

and an instruction retrieval control means for sending an instruction retrieval request.

data switching means for switching output data of the first and second cache memories;

configuration display means for displaying whether the first and second cache memories are connected or disconnected from the data processing device;

In response to the unconnected state of one of the cache memories displayed by the configuration display means, prohibiting the data switching means from selecting output data of the unconnected cache memory;
and a switching control means for permitting selection of output data of the cache memory in the other connected state.

In response to the unconnected state of one of the cache memories displayed by the configuration display means, a conflict between the operand fetch request and the instruction fetch request is detected when the two requests are sent to the cache memory in the other connected state. In this case, there is obtained a data processing device having request control means for sending one request to the cache memory in the other connected state in accordance with the priority set in the order of instruction fetch request and operand fetch request.

Further according to the invention.

In a data processing device having a cache memory.

Each includes a pair of a data array that stores data retrieved from the main storage means, and an address array that stores a correspondence between a storage address in the data array regarding the data and a storage address in the main storage means, each of which has a different address. and a second cache memory that can be selectively implemented in the data processing device.

operand fetching control means for sending an operand fetching request in response to an instruction register of the data processing device;

and an instruction retrieval control means for sending an instruction retrieval request.

data switching means for switching output data of the first and second cache memories;

A configuration display means for displaying whether each of the second cache memories is connected to or disconnected from the first data processing device.

In response to the unconnected state of the second cache memory displayed by the configuration display means, the data switching means prohibits selection of output data of the unconnected cache memory, and the data is in the first connected state. and a switching control means for allowing selection of output data of the cache memory.

When the operand fetch request and the instruction fetch request are sent to the cache memory in the first connected state in response to the unconnected state of the second cache memory displayed by the configuration display means, If a conflict is detected, the priority order is set in order of instruction fetch request and operand fetch request.

and request control means for sending both requests to the cache memory in the first connected state.

When the configuration display means displays an unconnected state of the second cache memory, data processing can be performed using only the first cache memory without installing the second cache memory in the data processing device. A device is obtained.

DESCRIPTION OF THE PREFERRED EMBODIMENTS [Detailed Description of the Invention] Next, the present invention will be described in detail with reference to the drawings. 1st
The figure is a block diagram showing an embodiment to which the present invention is applied.

In FIG. 1, instruction register 1 is an instruction code section opc.
It holds an instruction word consisting of , address deviation, and index designation part X. The index designation section X of the instruction register 1 designates one entry of the index register 2, which is made up of a plurality of entries. The address deviation and the output of the index register 2 are added in an operand address adder 5 to a pace register 3 that holds a pace address in virtual space to generate a virtual operand address. The instruction pre-fetch counter 4 holds the relative address in the virtual space of the instruction word to be pre-fetched, and counts 1 every time a fetch request is sent.
are added in increments.

The output of the instruction prefetch counter 4 is added to the pace address held by the pace register 3 in an instruction address adder 6 to generate a virtual address. The address switching circuit 7 outputs the output of the operand address adder 5 and the output of the instruction address adder 6 to the switching virtual address register 8. The output of the virtual address register 8 is connected to an address translation buffer (TLB) 9, in which it is translated into a real address, output to a real address register 10, and used to index the cache memory 11. The address switching means 12 switches between the output of the operand address adder 5 and the output of the instruction address adder 6, and outputs it to the virtual address register 13. The output of the virtual address register 13 is sent to the address translation buffer (TL
B) is connected to 14, is converted into a real address in address conversion buffer 14, and is output to real address register 15.

The output of the real address register 15 is sent to the cache memory 16.
used for indexing. Here, address translation buffers (TLB) 9 and 14 are each NEC technical report vol.
．． 35. Although it has the general configuration described in A5, detailed description thereof will be omitted since it has no direct connection with the present invention.

A detailed block diagram including the peripheral parts of the cage memory 11 and the cage memory 160 is shown in FIG. The real address register 1o and the real address register 15 each -
, real page addresses 10a and 15a, and column addresses 10b and 15b.

Holds intra-block addresses 10c and 15c.

The column address lOb of the real address register 1o reads out the real page addresses stored in the address array 101 of the cache memory 11 for the number of levels. These read real page addresses are processed by the comparator group 103.
A real page address 10a of the real address register 10,
compared in parallel.

A match is searched. The data in the data array 102 is read using part of the column address 10b and block address 10c in the real address register 1o, and the obtained data for the number of levels is controlled by the output of the comparator group 103. Data is selected and output from the level corresponding to the comparator selected by the selector 105 and detecting a match. If a match cannot be detected, the real address held in the real address register 10 is sent to the storage control unit 18, and the operation continues while replenishing the read data from the main memory MM. Cache-memory 16 is indexed by real address register 15. The cache memory 16 includes an address array 111, a data array 112 . It consists of a comparator group 113 and a selector 115, and their connections and operations are similar to those of the cache memory 11. In this way, you can use two cache memories.

- In a machine cycle, it is possible to obtain two different data, such as an operand and an instruction word. .

Referring again to FIG. 1, the data output of the cache memory II is directly transferred to the arithmetic execution section 19. The switching circuit 20 connects the cache memory 11 and the cache memory 1
Switch the data output of 6.

It is supplied to the instruction buffer 21. The instruction buffer 21 is a buffer memory that stores the instruction word transferred from the cache memory before completing the processing of the instruction existing in the instruction register 1. Similar to the switching circuit 20, the switching circuit 17 switches the data outputs of the cache memory 11 and the cache memory 16, and forms a path through which the data is transferred to the instruction register 1 by bypassing the instruction buffer 21 via the switching circuit 22. do.

FIG. 3 is a diagram showing a control circuit 100 related to sending out a cache-memory request in the embodiment shown in FIG. Operand fetch control section 50 decodes the instruction word held in instruction register 1 and outputs control signals 70 and 71. In this figure, a memory request signal 70 and a branch target fetching display signal 71 indicating whether the memory request is a branch instruction are shown. The instruction fetch control unit 51 uses the instruction prefetch counter 4 to output an instruction fetch request 72 while managing the empty state of the instruction buffer 21. The diagnostic control unit 52 manages the collection of data processing device failure information, command retry, and cache memory configuration control. This cache memory configuration control function is based on failure reports from cache memories 11 and 16 via signal lines 76 and 77 and system configuration information from external devices via signal line 78. This function determines connection or disconnection and outputs the second determination result to the cache configuration display 53. The cache configuration display 53 receives the determination result from the 1 diagnostic control unit 52 and determines whether each of the cache memories 11 and 16 is connected to the data processing device.

Displays whether it is in a disconnected state. The output 3 of this cache configuration display 53 is connected to the request control section 54 and the switching control section 5.
Sent to 5. The request control unit 54 is a core part of the present invention. This request control unit 54 handles various requests and cache configuration display capacity cuff 3. and two cages -
In response to the signals 74 and 75 indicating that each memory is in a request-acceptable state, a request that can be sent to the two cache memories is determined, and a signal is sent to the cache memory 11 via the signal line 80 and to the cache memory 16. Notification is made via line 81. At the same time, the request control unit 54 controls the switching circuit 7 via the control line 82 and the switching circuit 12 via the control line 83 in order to send the corresponding addresses to both cache memories. Also.

The request control unit 54 controls the cache memory when the request cannot be accepted or when a request conflict occurs.

A signal line 84 is sent to the request source, that is, the operand extraction control unit 50, indicating that the request cannot be sent. The instruction retrieval control section 51 is notified via the signal line 85, and the control section 50 or 51 that receives the notification holds the state until it is determined that the request can be sent. The switching control unit 55 responds to the control signal 90 of the operand retrieval control unit 50 and the output signal 73 of the cache configuration display 53, and connects the switching circuit 17 via the signal line 92 to the signal line 93.
is used to control the switching circuit 20 to select appropriate data from the two cache memories.

A control flowchart of the request control section 54 is shown in FIG.

The operation of the request control unit 54 shown in FIG. 3 will be explained below with reference also to FIG. When the signal line 73 instructs the connection of the cache memory 16, the request sent from the operand retrieval control unit 50 via the signal line 70 is sent to the cache memory IJ according to the branch destination prefetch instruction sent via the signal line 71. 11
t Send to one side of the cache memory 16. If the cache memory to be sent is in a state in which requests cannot be accepted, the operand retrieval control unit 50 is notified via the signal line 84. Furthermore, the output address of the land address adder 5 is sent via signal lines 82 and 83.

By controlling the switches 7 and 12, the data is sent to the cache memory 11 or 16. When the signal line 73 instructs disconnection of the cache memory 16, the request sent from the operand retrieval control unit 50 is output to the cache memory 11 regardless of whether it is a branch destination prefetch instruction or not. The instruction fetch request sent from the instruction fetch control unit 51 is received when the cache memory 16 is connected.

When a branch destination preemption instruction arrives from the operand retrieval control unit 5o, sending is suppressed due to request sending conflict.

Notifies the instruction fetching control unit 51 that the sending is not possible. If a branch target prefetch instruction does not arrive, an instruction prefetch request can be sent to the cache memory 16.

Sending of requests is controlled in accordance with a signal line 85 indicating the request sending enabled state of the cache memory 16. When the cache memory 16 is disconnected, the instruction fetch request is suppressed from being sent as a request from the operand fetch control unit 5o,
When there is no such request, a request is sent to the cache memory 11 in response to a signal line 75 indicating that the cache memory 11 is in a request-acceptable state. In addition, in a state where transmission cannot be accepted yet, the instruction fetching control section 51 is notified via the signal line 85.

A control flowchart of the switching control section 55 is shown in FIG.

The operation of the switching control section 55 in FIG. 3 will be described with reference to FIG. 5 as well. When the cache memory 16 is disconnected,
The switching circuit 17 and the switching circuit 20 are connected to the cache memory 1.
1 is fixed, and when the cache memory 16 is connected, the switching circuit 20 is set to select the cache memory 1.
1 is fixed to be selected, and the switching circuit 17 is enabled to select either the cache memory 11 or the cache memory 16 according to an instruction from the control line 90. Here control line 9
0 is used when fetching an operand by referring to data other than the instruction word, such as in an indirect address modification operation.

In the above description, the disconnection and connection of the cache memory 16 are described, but by providing a switch similar to the switch 20 in the preceding stage of the calculation execution unit 19, the cache memory 11 can be disconnected. .

The cache memory 16 can be operated as an alternative cache memory.

Further, since the cache configuration display 53 is fixedly disconnected from all input/output signals to one memory by the signal 78 (FIG. 3) from the external device, the disconnected cache memory can be deleted from the device. be. Similarly, address translation buffers, real address registers, and virtual address registers can also be deleted. This function allows a slower data processing device to be easily realized at a lower cost than a high speed data processing device having two cache memories.

According to the request control unit 54 described above, it is possible to operate the cache memory 16 by separating it, but as shown in FIG. 4, when one cache memory is in operation, requests are sent by giving priority to operand fetch requests over instruction fetch requests. There is. If this priority order is followed, replenishment of instruction words will be delayed due to fetching of operands, and the processing line will not move smoothly. 7 when the instruction supply is 2 instructions/request and the instruction buffer capacity is 4 instructions
FIG. 6 shows the four-line operation. In FIG.

A is a virtual address generation cycle, P is a paging cycle, C is a cache cycle, E is an operation execution cycle,
W indicates the result storage cycle. According to FIG. 6, the arithmetic execution unit 19 is in an idle state for 3 out of 7 machine cycles even when operating at the highest speed.

Next, FIG. 7 shows a control flowchart of the request control section 54 which has been improved so that an instruction fetch request has priority over a normal operand fetch request in an operating state with the cache memory 16 disconnected. According to FIG. 7, when the signal line 73 instructs to disconnect the cache memory 16, if the request sent from the operand retrieval control unit 50 via the signal line 70 is a branch destination prefetch instruction, the signal line 72 is The output of the address adder 5 is sent together with the request to the cache-memo IJ 1 i regardless of whether there is an instruction fetch request sent via the cache memory IJ 1 i.

If it is not a branch target prefetching instruction, that is, a normal operand fetching request, and there is an instruction fetching request sent via the signal line 72, the output of the adder 5 to the cache memory 11 and the sending of the request are suppressed, and the signal line 84 is If there is no instruction fetch request, the adder 5 output and the request are immediately sent to the cache memory 11.

On the other hand, an instruction retrieval request that is not sent from the instruction retrieval control unit 51 via the control line 72 is transmitted between the signal line 70 and the signal line 71 when the signal a73 instructs disconnection of the cache memory 16.
If the operand fetching control unit 50 is sending out a branch destination preemption request via the signal line 85, the operand fetching control unit 50 sends the branch destination preemption request with priority, and notifies the instruction fetching control unit 51 via the signal line 85 that the request sending is not completed. do. If the request is not sent from the operand fetch control unit 50 or if it is a normal operand fetch request that is not a branch destination prefetch request, the output of the address adder 6 is output to the cache memory 11 via the signal line 82. It controls the switch 7 and notifies the cache memory 11 of a request via the control line 80.

FIG. 8 shows the operation of the second improved request control unit. According to FIG. 8, in order to smoothly execute instruction retrieval, the arithmetic execution unit 19 can execute two out of three machine cycle operations, improving performance by 16 times compared to the conventional system. Also.

As shown in the flowchart of FIG. 7, the priority of a request to preempt a branch destination of a branch instruction is set higher than that of an instruction fetch request, regardless of the 2 cache memory/1 cache memory configuration, so that This avoids deterioration in instruction performance.

[Detailed description of the invention]

As described above, the present invention includes a request control means.

By providing the switching control means, there is an effect that the operability can be improved while minimizing performance deterioration in a data processing apparatus having two cache memories.

Furthermore, the present invention provides a low-cost medium-speed data processing system that operates with one cache memory as a sub-model of a high-speed data processing device employing two cache memories by providing a request control means and a switching control means. This has the effect that the device can be easily realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data processing device to which the present invention is applied, FIG. 2 is a detailed block diagram of cache memories 11 and 16 shown in FIG. 1, and FIG. 3 is a control circuit in the data processing device of FIG. 1. 100, FIG. 4 is a diagram showing a control flowchart of the request control unit 54 of FIG. 3, which is the basis of the present invention, and FIG. 5 is a detailed block diagram of the switching control unit 55 of FIG.
FIG. 6 is a diagram showing a time chart of the data processing device according to the control shown in FIG.
FIG. 7 is a diagram showing a control flowchart of the request control section 54 of FIG. 3 according to the present invention, and FIG. 8 is a diagram showing a time chart of the data processing apparatus according to the control of FIG. 7. 1...Instruction register, 2...Index register. 3...Base register, 4...Instruction counter, 5.
...Operand address adder, 6...Instruction address adder, 7 and 12...Address switching circuit, 8 and 1
3... Virtual address register, 9 and 14... Address conversion buffer, 10 and 15... Real address register, 11 and 16... Cache memory, 17 and 20... Switching circuit, 21. ...Instruction buffer, 22
... switching circuit, MM... main memory, 50... operand fetching control section, 51... instruction fetching control section, 52...
・Diagnostic control unit. 53... Catch-configuration display, 54... Request control unit. Figure 5 Figure 6 Idol 4 big a1'' 74 strokes I cycle 3 wallet I and 3 gamma orgasms

Claims (1)

[Claims] (1) In a data processing device having a cache memory. Each pair includes a data array that stores data retrieved from the main storage means, and an address array that stores a correspondence between a storage address in the data array and a storage address in the main storage means regarding the data, and each has a different pair. first and second cache memories capable of responding to addresses; operand fetching control means for sending an operand fetching request in response to an instruction register of the data processing device; and an instruction fetching control means for issuing instructions and sending out requests. data switching means for switching output data of the first and second cache memories; configuration display means for displaying whether the first and second cache memories are connected or disconnected from the data processing device; In response to the unconnected state of one of the cache memories displayed by the configuration display means, prohibiting the data switching means from selecting output data of the unconnected cache memory;
and a switching control means for permitting selection of output data of the cache memory in the other connected state. In response to the unconnected state of one of the cache memories displayed by the configuration display means, a conflict between the operand fetch request and the instruction fetch request is detected when the two requests are sent to the cache memory in the other connected state. and request control means for sending one request to a cache memory in the other connected state according to a set priority in the order of an instruction fetch request and an operand fetch request. 2. In a data processing device having a cache memory. a data array for storing data retrieved from the main storage means; and an address array for storing a correspondence between a storage address in the data array and a storage address in the main storage means for the data; a first cache memory capable of responding to different addresses; and a second cache memory selectively implementable in the data processing device. Operand fetch control means for sending an operand fetch priority in response to an instruction register of the data processing device. and an instruction retrieval control means for sending an instruction retrieval request. data switching means for switching output data of the first and second cache memories; and configuration display means for displaying whether each of the second cache memories is connected or disconnected from the data processing device. In response to the unconnected state of the second cache memory displayed by the configuration display means, the data switching means prohibits selection of output data of the unconnected cache memory, and the data is in the first connected state. A switching control means for selecting output data of the cache memory. When the operand fetch request and the instruction fetch request are sent to the cache memory in the first connected state in response to the unconnected state of the second cache memory displayed by the configuration display means, If a conflict is detected, the priority order is set in order of instruction fetch request and operand fetch request. and request control means for sending both requests to the cache memory in the first connection state. When the configuration display means displays an unconnected state of the second cache memory, data processing can be performed using only the first cache memory without installing the second cache memory in the data processing device. Device.