JPS6025909B2 - semiconductor equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate field effect semiconductor device that realizes a nonvolatile random access memory.

Memory devices with a semiconductor integrated circuit structure (IC memory) have always had high density, large integration, and low power consumption as their development philosophy.

Also, the memory function stores information “1” and “0” at the selected address.
Random access memory (RAM) is ideal in terms of versatility. Traditionally, RAM-type IC memories have been constructed using flip-flops, dynamic MOS transistors (3-element type), and C-load type IMOS transistors (I
Tr type) has been put into practical use as a memory cell.
However, not only are the circuit structures of these IC memory devices complex, but also power consumption is required to retain information, which essentially limits their ability to achieve high density and large scale integration. A nonvolatile memory that injects and stores charges into a trap center or a floating gate in an insulated gate film and utilizes the nonvolatility of the stored charges is expected to be a memory cell that may solve this problem.

Although such known non-volatile memory does not require power consumption to retain information, it
It is not useful as a RAM because it is necessary to change the address selection method when writing ``, and the information to be selectively written is either ``1'' or ``0'', and the other is all bits. According to the conventional technology, non-volatile RAM, which is required as a modern function of IC memory, has been developed as a programmable read-only memory (PROM). there were.

An object of the present invention is to provide a semiconductor device that realizes a nonvolatile RAM with high density, large integration, and low power consumption.

A feature of the present invention is that in a semiconductor device in which a series circuit of a decode transistor and a memory transistor whose gate threshold value is transferred is arranged at each matrix intersection where matrix lines intersect, A part of the junction has a lower breakdown voltage than the junction between the other part of the drain or source region and the substrate, and the gate electrodes of these memory transistors are each connected in common to the semiconductor device.

Still another feature is that first and second field effect transistors having source and drain regions of opposite conductivity type are provided on a semiconductor substrate of one conductivity type, and these first and second field effect transistors are connected to the semiconductor substrate of one conductivity type. In a semiconductor device in which regions of opposite conductivity type provided on a semiconductor substrate are connected in series and a high concentration region of one conductivity type is formed in contact with the source and drain regions of only this first field effect transistor, this first electric field The effect transistor is a memory transistor in which the gate voltage transitions, and each gate electrode of the first field effect transistor in parentheses is located in a semiconductor device that is commonly connected. According to this invention, a series circuit of a decode transistor and a memory transistor having a floating gate is arranged as a memory cell arranged at a matrix intersection, and a series circuit of a decode transistor and a memory transistor having a floating gate is arranged between the floating gate of the memory transistor and a semiconductor substrate. A semiconductor device is obtained in which a second insulating film that generates a stronger electric field than the first insulating film is provided, and a gate electrode is provided as an information line common to the matrix.

The electric field effect on the insulating film is proportional to the exposure density. Therefore, the electric field in the first and second insulating films is controlled by their mutual dielectric ratio or coupling capacitance configuration. In the semiconductor device of the present invention, the memory cell is composed of only two transistors, and information "0" and information "1" can be selectively written to a selected address by controlling the information signal line as described later. In addition, since the memory transistor is a non-volatile memory, the peripheral circuit configuration of the memory section and the circuit configuration of the memory cell itself are extremely simple, making it easy to achieve high density and large integration in RAM.
This makes it possible to reduce power consumption during the information retention period to zero.

Therefore, according to the present invention, since the memory transistors and decode transistors are arranged at each matrix intersection, each memory transistor can be selected at high speed, and furthermore, the memory transistors can be dropped at a lower voltage than the decode transistors. Therefore, these transistors can be made into extremely 4-type transistors using the same process.

Since each memory transistor can be selected by each decode transistor, there is no need to select the gate of each memory transistor, and therefore, a high-voltage selection transistor is completely unnecessary. Next, in order to better understand the present invention, embodiments of the present invention will be described using figures.

FIGS. 1A and 1B' show a circuit diagram and a sectional view of a memory cell according to an embodiment of the present invention.

In this embodiment, a series circuit consisting of a decode transistor Qo and a memory transistor QM is introduced as a memory cell at each intersection of a matrix formed by row lines D, , D2 and column lines W, , W2. This series circuit is a decode transistor Q. The gate electrode of
, one of the drain and source is connected to a predetermined row line D, and the other is connected to one of the drain and source of the memory transistor QM, and the other of the drain and source of the memory transistor QM is connected to the reference line GND, and the gate electrode is connected to each address. It is connected to a common information line DL together with the memory transistors. In addition, the base electrode S of all transistors
UB is common, and a predetermined bias is applied between it and the reference line GND. A preferred integrated circuit structure of the memory cell has a resistivity of 100 with a main surface of 100 as shown in FIG. 1B.
P-type region 1 with a surface concentration of 8 x 1 and 5 to 5 x 1 and 6 skin-3 in the inactive part of one surface of Ichigo's P-type silicon single crystal 101
02, and the active region surrounded by this region is subjected to phosphorus diffusion with a surface concentration of 1 pio to 1 p1 -3 to form an N+ type region 103,
104, 105 are provided, and aluminum electrode wirings 107, 109, 10 extending over the top surface of the surface insulating protective film 106 are provided.
It has 9,110.

An insulating film 111 of about 500A of boron dioxide deposited on the surface of the active part of the base 101, N+ type regions 103 and 104 of the drain and source, and the electrode wiring 1 on the left side of FIG. 1B.
Polycrystalline silicon gate electrode 112 conductively connected to 09
constitutes an insulated gate decode transistor Qo, and N
Leading electrode wiring 107 from ten-shaped region 103 is connected to row line D, and electrode wiring 108 is connected to column line W. In addition, a surface concentration of 5×1 and 6 is formed in contact with the insulating film 111, the N-type regions 104 and 105 that become the drain and source, and a part of the N+-type region 104 to form a PN diode with a low breakdown voltage.
~1 and 6-3 P+ type region 1 13 and insulating coating 11
1, and a floating gate 115 embedded in the boundary between these insulating films.
A nonvolatile memory transistor Q is configured with a gate electrode 109 capacitively coupled to the floating gate 115 via another insulating film 114, and the gate electrode 109 is connected to the information line DL, and the lead electrode wiring 110 of the N+ type region 105 is connected to the information line DL. is connected to the reference line GND, and the N+ region 104 is used as a common region for the decode transistor and the memory transistor to form a series circuit. A base electrode 116 is provided on the back surface of the base 101 and serves as a base terminal SUB. FIG. 2 is a graph showing the electrical characteristics of the memory transistor of the embodiment shown in FIG.

An N-channel memory transistor having a floating gate has an M1, M12S type gate structure consisting of an outer gate electrode, an insulating film, a floating gate, an insulating film, and a semiconductor substrate, and an insulating film 1 between the floating gate and the gate electrode. , determines the usefulness of a memory transistor for RAM use. That is, source potential Vs, drain potential VD
, with respect to the base potential Vsub and the gate electrode potential VG,
Vs=V. =Vs = OV, and after applying voltage to VG for about 1 second, the gate threshold value VT of the memory transistor is determined.
is measured and the relationship between VT and VG is shown in Figure 2.
In the memory transistor structure shown in Figure B, using a silicon dioxide film formed by 12K thermal oxidation, and using silicon nitride film formed by vapor phase growth in 1., the initial VT is as shown in characteristic curve a. Accumulate negative charge with a critical value +Vc of 150V for positive Vc,
It exhibits an indirect tunnel injection type charge storage function that releases negative charges with a critical value of -Vc at -40V. Similarly, when an alumina film is used for 1 and 1, indirect tunnel injection type characteristic curves are given with critical values of 150V and 140V.

However, if a silicon dioxide film obtained by thermal oxidation of polycrystalline silicon used for the floating gate is used in step 1, an ion drift type characteristic as shown in characteristic curve C can be obtained. These characteristics are controlled by the insulation constant and dielectric constant of 1, and in this invention, the information “1” and “0”
It is not preferable to use an insulator whose VT-VG characteristics have a higher and more stable critical value than the control voltage of the information line. For example, it is preferable to use silicon nitride, alumina, tantalum oxide, zirconium oxide, or titanium oxide for the 1st and 121st substrates, and to use a thermal oxide for the 121st substrate. In addition, in the memory cell in which a silicon nitride film or alumina film is used for the IA of this embodiment, when a predetermined matrix line is selected and the low breakdown voltage diode directly under the floating gate is broken down, the critical value of the injection type is +Vc and -Vc. b′
give. These characteristic curves a' and b'' are a kind of avalanche injection operation that occurs because electrons and holes generated by avalanche breakdown in the reverse direction of the diode are drawn toward the floating gate in accordance with the gate electric field. By using this characteristic curve b', it is possible to selectively write information "1" or "0" into the memory cell at the selected address simply by controlling the potential of the gate electrode of the memory transistor. At other addresses, the decode transistor does not function, so diode breakdown does not occur, and a voltage below the critical value is simply applied to the gate electrode of the memory transistor, so information is not disturbed. FIG. 3 shows voltage waveforms for selective write/read operations in the embodiments described above.

Selection of an address is performed by applying a driving voltage V to the matrix line to the address.
o, Vw, and control the potential Vo of the information line to obtain information "
1" or "0" is selectively written, and the current flowing from the column line through the memory cell is received as the output lout. In other words, the substrate is kept at the potential of OV, and the address selected at time t. Drive voltage Vo9Vw of about 30V
is applied, the potential VoL of the information line is about 30V, and the reference line GN
When D is cut off from the circuit tangent or raised to about +10V with respect to the substrate, the memory transistor becomes non-conductive and the low voltage diode formed in a part of the N-type region of the memory transistor at the selected address becomes avalanche at about 115V. Surrender. At this breakdown point, an electric field is applied at the potential of the information line to induce negative charges from the gate electrode of the memory transistor, and therefore electrons are injected from the breakdown point toward the floating gate. In memory transistors at other addresses that are not selected at this time, the decode transistors are non-conductive or even if they are conductive, the potential of the N-type region of the memory transistor is OV, so the diodes at addresses that are not selected are A breakdown phenomenon does not occur, and no charge is transferred to or from the floating gate for transferring the gate threshold value of the memory transistor. Due to this selective writing, negative charges are accumulated in the floating gate, and the gate voltage of the memory transistor is shifted to the positive direction by about 8V. If information writing due to an increase in gate threshold value is defined as information “0”, then this information “
0'' is the driving voltage Vo of 15V during the period from time t3 to
By applying Vw to the matrix line to the same address and simultaneously applying a potential VoL of 15V to the information line, a "0" output current from the address can be obtained. The "0" output current is a zero current because the gate threshold value of the memory transistor is higher than the potential VoL as a read signal. Also, Time et al ~ t6
When applying drive voltages Vo and Vw of approximately 130V to the matrix line at the selected address at time , as in the case of writing information "0", and at the same time setting the potential VoL of the information line from 0 to 120V, the information at this address is Positive charge accumulation is induced in the floating gate of the memory transistor, the gate threshold value decreases, and information "1" is selectively written. This writing of information "1" occurs because the low breakdown voltage diode of the memory transistor at the selected address undergoes avalanche breakdown, and because the potential of the gate electrode is low, an electric field acts that draws holes toward the floating gate.
When information "0" is written in the memory transistor at the address, the information is rapidly changed to "1".
Further, the transition of the gate function value of information "1" in the negative direction is controlled by the potential of the gate electrode, and when the potential of the information line is set to OV and the signal for writing information "1" is used, the gate function value of the memory transistor becomes -. It becomes 1 to 10 IV, and if it is -20V, -1
~-5V, and the level of information "1" can be controlled. At time t8, the selective read operation is performed again in the same manner as at time t4, and the drive voltage VD of 10 W is applied to the selected address.
, Vw, and at the same time the information line is driven with 10 W, the memory transistor in which the information "1" is written is in a conductive state because the gate threshold value is 5 V or less, and the reference signal from the row line to the address is A “1” output current flowing through the line can be obtained.

The operation of selective writing and selective writing of the RAM in one embodiment of the present invention has been explained above.
This uses a nonvolatile memory having an insulated gate film structure that does not cause intersellar tunnel injection or ion drift to memory transistors at unselected addresses at the potential of the information line that provides information "0", and the insulating film on the floating gate. It is preferable to use a silicon nitride film or a metal oxide film grown in a vapor phase either alone or in a stacked layer with a silicon dioxide film.

Furthermore, although a silicon dioxide film is generally used as the insulating film under the floating gate, a silicon nitride film or a metal oxide film can be used alone or in a double layer with silicon dioxide, if necessary. N+ directly below the floating gate of the memory transistor
The low breakdown voltage diode formed in the type region is provided at least in a portion of one of the drain and source, and has reverse breakdown voltage characteristics lower than the drain junction breakdown voltage of the decode transistor. For this reason, the diode is formed not only by bringing the highly doped P-type region into contact with the N+-type region as in the previous embodiment, but also by making the insulating film between the floating gate and the substrate thinner than the insulating gate film of the decode transistor. Favorable properties can be obtained even if Furthermore, the potential of the information line for writing information "1" does not necessarily require a negative voltage, and information "0" in the memory transistor can be selectively rewritten to information "1". When the potential of the information line and the diode withstand voltage are set so that the gate threshold value of the memory transistor by writing information "1" is in the depletion region and the gate dark value by writing information "0" is in the enhancement region, the read operation is not possible. The potential of the information line can be set to the same potential as the reference line.

[Brief explanation of the drawing]

1A and 1B are a circuit diagram and a cross-sectional view of a memory cell according to an embodiment of the present invention, FIG. 2 is a VT-VG characteristic diagram illustrating the effects of the present invention, and FIG. 3 is an embodiment of the present invention. It is a voltage waveform diagram showing the operation of an example, where Qo is a decode transistor, QN is a memory transistor, D,, D2 are row lines, W,, W2 are column lines, DL is an information line, GND is a reference line,
SUB is a base electrode, 101 is a P-type silicon single crystal, 1
03, 104, 105 are N+ type regions, 111 and 11
4 is an insulating film, and 115 is a floating gate. Figure 1 (A) Figure 1 B) Figure 2 Figure 3

Claims (1)

[Claims] 1. In a semiconductor device in which a memory cell is constituted by a decode transistor and a memory transistor whose gate threshold changes, and each memory cell is arranged at an intersection where matrix lines intersect, the memory cell is of one conductivity type. first, second and third regions of opposite conductivity types provided on a semiconductor substrate, the first region and the second region being one and the other of the source and drain regions of the decode transistor; The second region and the third region are one and the other of the source and drain regions of the memory transistor, and the first region of each memory cell is commonly connected in the row direction, and the first region of each memory cell is connected in common in the row direction. The gates of the decode transistors are commonly connected in the column direction, and a part of the PN junction between the second region and the substrate on the side opposite to the third region is connected to the other part of the second region. The memory transistor has a lower breakdown voltage than a PN junction with a substrate, and the memory transistor includes a silicon dioxide film provided on the substrate between the second region and the third region, and a floating gate provided on the silicon dioxide film. , providing an insulating film having a silicon nitride film or a metal oxide film on the floating gate,
A semiconductor device characterized by having a structure in which a gate electrode is provided on the insulating film.