JPS6047343U - 3 phase solid state relay - Google Patents

3 phase solid state relay

Info

Publication number
JPS6047343U
JPS6047343U JP14001783U JP14001783U JPS6047343U JP S6047343 U JPS6047343 U JP S6047343U JP 14001783 U JP14001783 U JP 14001783U JP 14001783 U JP14001783 U JP 14001783U JP S6047343 U JPS6047343 U JP S6047343U
Authority
JP
Japan
Prior art keywords
terminals
phase
main terminals
main
element circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14001783U
Other languages
Japanese (ja)
Other versions
JPH0246118Y2 (en
Inventor
大島 征一
山下 信三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP14001783U priority Critical patent/JPS6047343U/en
Publication of JPS6047343U publication Critical patent/JPS6047343U/en
Application granted granted Critical
Publication of JPH0246118Y2 publication Critical patent/JPH0246118Y2/ja
Granted legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は単相SSRの主端子回路の回路図、第2図at
 bはそれぞれ本考案の一実施例による3相SSRの平
面図及び左側面図、第3図at bは第2図に示す3相
SSRの一部拡大平面図及びその正面図、第4図は第2
図に示す3相SSRの使用状態を説明するための図であ
る。 11、 12. 13・・・主端子、14. 15. 
16・・・ゲート中継端子、17・・・出力バリヤ、2
0・・・制御回路部(制御回路)、22.23.24・
・・制御回路の出力端子、62・・・3相交流電源、6
3・・・モータ(負荷)、80・・・半導体主素子回路
。なお図中同一符号は同−又は相当部分を示す。 第1図 第3図
Figure 1 is a circuit diagram of the main terminal circuit of a single-phase SSR, Figure 2 at
b is a plan view and a left side view of a three-phase SSR according to an embodiment of the present invention, FIG. 3 at b is a partially enlarged plan view and a front view of the three-phase SSR shown in FIG. 2, and FIG. Second
FIG. 3 is a diagram for explaining the usage state of the three-phase SSR shown in the figure. 11, 12. 13... Main terminal, 14. 15.
16... Gate relay terminal, 17... Output barrier, 2
0...Control circuit section (control circuit), 22.23.24.
...Control circuit output terminal, 62...3-phase AC power supply, 6
3...Motor (load), 80...Semiconductor main element circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts. Figure 1 Figure 3

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 3相交流電源の負荷への供給を接断するための3つの半
導体主素子回路と、該半導体主素子回路をオン・オフ制
御する制御回路とを備えた3相ソリツドステートリレー
であって、上記3つの半導体主素子回路の電源側主端子
および負荷側主端子は各相の電源側主端子と負荷側主端
子とが相互に対向し、それぞれ3つの電源側主端子及び
負荷側主端子が相互に平行な直線上に順に並ぶように配
設され、上記3つの半導体主素子回路と上記制御回路の
出力端子とを接断する3対のゲート中継端子は上記各主
端子と同1上に該名主端子と交互に配設され、上記各主
端子と該名主端子に隣接するゲート中継端子との間には
該両端子間の絶縁距離を確保するための出力バリヤが設
けられていることを特徴とする3相ソリツドステートリ
レー。
A three-phase solid-state relay comprising three semiconductor main element circuits for connecting and disconnecting the supply of three-phase AC power to a load, and a control circuit for controlling on/off of the semiconductor main element circuits, The power supply side main terminals and load side main terminals of each phase of the above three semiconductor main element circuits face each other, and the three power supply side main terminals and load side main terminals of each phase face each other. Three pairs of gate relay terminals, which are arranged in order on straight lines parallel to each other and connect and disconnect the three semiconductor main element circuits and the output terminal of the control circuit, are arranged on the same plane as each of the main terminals. Output barriers are arranged alternately with the main terminals and are provided between each of the main terminals and a gate relay terminal adjacent to the main terminals to ensure an insulating distance between the two terminals. A three-phase solid state relay characterized by:
JP14001783U 1983-09-08 1983-09-08 3 phase solid state relay Granted JPS6047343U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14001783U JPS6047343U (en) 1983-09-08 1983-09-08 3 phase solid state relay

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14001783U JPS6047343U (en) 1983-09-08 1983-09-08 3 phase solid state relay

Publications (2)

Publication Number Publication Date
JPS6047343U true JPS6047343U (en) 1985-04-03
JPH0246118Y2 JPH0246118Y2 (en) 1990-12-05

Family

ID=30313637

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14001783U Granted JPS6047343U (en) 1983-09-08 1983-09-08 3 phase solid state relay

Country Status (1)

Country Link
JP (1) JPS6047343U (en)

Also Published As

Publication number Publication date
JPH0246118Y2 (en) 1990-12-05

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