JPS6058662A - Memory device for temporary storage of charge - Google Patents

Abstract

PURPOSE:To obtain the unit cell of the DRAM suitable for increasing the density and the capacitance by a method wherein the upper surface of a pedestal-form single crystal Si is provided with at least part of a switching MISFET, and a capacitor is provided by including at least part of the pedestal side surface. CONSTITUTION:A P type Si substrate 300 is provided with a thermal oxide film 301, and then a stepwise difference is formed by photoetching. Boron is thermally diffused with the film 301 as a mask, and accordingly a P<+> layer 302 is formed on the side surface of the stepwise difference and the etched bottom. Next, a window is opened 303 in the film 301 of the upper surface of the trapezoid and then covered with oxide thin films 304 and 305, a window 306 being selectively opened, and phosphorus-contained poly Si 307 being attached by the CVD method. The poly Si 307 is selectively left by sputter etching with a reactive gas after application of a resin mask. Then, an n-layer 308 is formed by the implantation of phosphorus ions. This constitution produces a micro occupation area on the plane of a capacitor and enables to secure a capacitance value necessary for the countermeasure against alpha rays, leading to the increase in strength to alpha rays. Accordingly, many memory elements for temporary storage of charges can be formed in a micro area.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit storage device, more specifically,
An MIS type charge temporary storage storage device (hereinafter referred to as DRAM) consisting of one transistor and one capacitor.
(dynamic random access
It is abbreviated as "emory". ) Conventionally, an MO consisting of one transistor and one capacitor
8-inch DRAM has a small number of elements, so it can be easily integrated at high density, making it an inexpensive storage device.

It is becoming widely used. However, in order to improve the mounting density on a printed circuit board, the size of the cage is limited, and the size of the semiconductor chip is also limited, and the maximum allowable limit is said to be about 40 mm. From this, for example, in a 1 megapitch chip, the area of 1 pip is 20 to 30 μm'. Approximately half of this area is used for transistors and isolation between elements, so the capacitor is only allowed an area of about 10 to 15 microns on a plane. If an attempt is made to form a capacitance of 50 fF or more with this area using a silicon oxide film to prevent malfunctions due to alpha rays, the film thickness will be 70X or less. It is extremely difficult to form such a thin oxide film, but even if a good insulating film with no pinholes could be formed, if a 5V power supply is used, the insulating film will be 7M
It must operate under a high electric field of about V/cm.
A state is reached in which current flows from the gate or the silicon substrate.

With the simple structure that has been used in the past, it is difficult to obtain a highly reliable storage device with a sufficiently large capacitance that can withstand alpha rays.
Now, it is theoretically impossible. Therefore, in order to increase the area occupied by the capacitor within the chip, methods are being considered to reduce the isolation area between elements. This includes:
Mizohori separation.

New separation techniques such as selective epitaxial separation have been proposed. Further, as a DRAM storage capacitor related to the present invention, a conventional DRAM as shown in FIG.
An idea has been announced to increase the effective area by drilling a deep hole in the carburetor part of M, as shown in Figure 2. This idea is excellent because it increases capacitance and enables high density and large capacity.

However, the semiconductor surface of this capacitor is nya.

Since the substrate is used at pm, it has the effect of collecting electrons of the electron-hole pairs generated when α rays pass near the capacitor on the surface of the semiconductor that becomes the capacitor. In addition to the increased effective area of conventional perforated DRAMs, this effect line also has the disadvantage that it reliably collects electrons generated by alpha rays and is prone to malfunction. Furthermore, it is difficult in principle to bring the grooves of adjacent capacitors close to each other because the depletion layer expands. This has the disadvantage that the separation width between the capacitors must be widened.

The purpose of the present invention is to obtain a large capacitance with a small internal chip and a limited area, while being resistant to alpha rays, and also reducing the distance between capacitors to the minimum size possible with exposure technology, processing technology, and chipping technology. DRA suitable for high-density and large-capacity
The present invention provides M storage unit elements (hereinafter sometimes referred to as cells) and an integration method suitable therefor.

The DRAM cell according to the present invention has one switching MIS.
A type field effect transistor is formed at least partially on the upper surface of a semiconductor single crystal formed on a pedestal, and a capacitor for storing charge is formed including at least a part of the side surface of the pedestal. .

Next, the effects and advantages of the present invention will be described in detail using a first embodiment of the present invention.

FIG. 3 is a schematic diagram showing the first embodiment of the present invention.
(a) is a plan view thereof, and (b) is a cross-sectional view taken along the dashed line in the figure (1). In FIG. 3, only one cell portion from the transistor gate electrode to the upper electrode of the capacitor is shown. In order to integrate this, it is necessary to separate a large number of these cells and interconnect them together with the drive circuit, but this is not shown here. Next, we will describe the features of the severe cases while describing an example of the manufacturing process. First, a p-type single crystal silicon substrate 300 of about 5Ω・m is coated with a thickness of about 5oooX.
A thermal oxide film 301 is formed, and the oxide film 301 and the substrate 300 are successively etched and etched using a re-etching method to form a step of about 2 μm. Further, using this oxide film 301 as a mask, boron (B) is thermally diffused to form a p+ impurity layer 302 on the side surfaces of the step and the etched bottom surface.

Next, a portion 303 of the oxide film on the upper surface of the trapezoid where a transistor will be formed is removed by photolithography, and then thermal oxidation is performed to form thin oxide films 304 and 305 with a thickness of about 20 OA. Following that, the part 3 that becomes the drain of the transistor
Only in 06, this thin oxide film was removed. Next, Lin ψ)
Alternatively, polysilicon 307 containing high-purity NFI impurities of arsenic (As) was deposited by chemical vapor deposition (CVD).

As shown in the figure, the gate area and the vicinity of the drain are covered with a photosensitive resin (resist), and sputter etching is performed using a reactive gas such as CCT4.5TC4.

Polysilicon can be left only on the area covered with resist and on one side of the trapezoid. Thereafter, by using ion implantation to form an n-type impurity region of phosphorus or arsenic in the transistor active region near the gate, the memory element of the first embodiment shown in FIG. 3 is obtained. As can be seen from the figure, since the capacitor is formed on the side surface of the step, the capacitor occupies only an extremely small area within the plane. It is no exaggeration to say that it is actually the area of one transistor. If the planar area of the transistor is 4 x 6 μm, each level difference is 2 μm, and the thickness of the thin oxide film formed on the side surfaces is 25 OA, a capacitance 1 of approximately 66 fF can be obtained only on the side surfaces, which is a countermeasure against alpha rays. The required 50fF can be secured.

In addition, since the capacitor does not have a pn junction with the substrate, it also has resistance to alpha rays, and the applied voltage can be reduced to 5.
If v, the oxide film at this time is also exposed to only the maximum driving electric field of 2 MV/sub, so complete insulation can be maintained. As described above, it has been found that by using the present invention, a large number of charge temporary storage storage elements can be formed in a small area.

FIG. 4 shows a second embodiment of the present invention, which is similar to the first embodiment, but uses a selective oxidation method using a silicon nitride film to determine the transistor region.

First, as shown in FIG.
After forming 03, the silicon oxide film and nitride film are removed by a photolithography process. Subsequently, a P-type impurity such as boron (B) is implanted into the removed area by ion implantation or the like to form a channel strike or bar layer 404 for preventing surface inversion.

Then (b) as shown in figure ? Next, a so-called field oxide film 405 is grown to a thickness of about 0.6 μm by thermal oxidation.

Subsequently, as shown in figure (c), a reactive layer is applied to the field area around the transistor.

A groove with a depth of 1 to 2 μm and a width of 1 μm is formed. Then, a p-type layer 406 is formed by diffusing impurities such as boron at a high concentration.

Next, a silicon nitride film 403 is left on the surface of the portion that will become the transistor active region. The silicon oxide film 402 is removed, and a gate insulating film 408 is formed again as shown in FIG.
A capacitor partial insulating film 409 is formed. Thereafter, a boron ion implantation layer 410 is formed to control the one-value voltage at the gate of the transistor.

Subsequently, a direct contact window 411 is opened.

Then, as shown in the (-) figure, polysilicon 412 is deposited to a thickness of about 0.5 μm, enough to completely fill the groove.

Next, an n-type impurity such as phosphorus (P) is diffused into the polysilicon and the direct contact portion. Next, after etching the polysilicon so that the gate 414 of the transistor and the direct contact are connected to the capacitor trench, an impurity layer 4 of the source and drain portions of the transistor is formed by ion implantation of phosphorus (ψ) or arsenic (As).
15 is formed (f) a cross section as shown in the figure and 0)
A plane as shown in the figure is obtained.

In this second embodiment, compared to the first embodiment, all of the transistors in the memory driving peripheral circuit section other than the memory section can be separated by the conventional selective oxidation method, and the transistors are not stored in the conventional memory element. It has the advantage that many of the technologies described above can be used as is.

Also in this embodiment, since the capacitance is large and does not have a pn junction with the substrate, it has sufficient resistance to α rays.

In the first and second embodiments described above, the capacitor was formed so as to completely surround the transistor.

The invention does not necessarily require this. FIG. 5 is a plan view showing a third embodiment of the present invention, which is an example in which a capacitor is removed from the source side of the second embodiment and the source is used as a bit line. FIG. 6 is a plan view showing a fourth embodiment of the present invention in which a capacitor is formed only around the drain.
This is an example in which the sources of every other memory element arranged in the vertical direction of the figure are connected to form a bit line.

The embodiment described above has been described in which an impurity region having the same conductivity type as that of the silicon substrate is provided on the silicon surface of the sidewall surface or the bottom surface, but the present invention may be applied to an impurity region having the opposite conductivity type. In Figure 7.

A fifth embodiment of the present invention is shown. Here (-) is 弽)Figure A
A p+ type layer 710 of a channel stopper in the field portion was formed on a p type substrate 701, which is a cross-sectional view taken along line B from 1 to 7, according to the fourth manufacturing process shown in the second embodiment. The trench silicon surface 711 is made n-type by diffusing the impurity phosphorus ψ). After etching the gate polysilicon, a planar polysilicon etching pattern may be selected so that this n-type part is connected to the n+ part of the drain formed by ion implantation.

In the first to fifth embodiments described above, an example is shown in which an n-channel transistor is provided with a silicon substrate having p-type conductivity. However, it does not matter even if it is a p-channel type, and in this case, all impurity layers formed on the surface may have opposite conductivity types.

Furthermore, in the manufacturing method of the embodiment described above, the polysilicon buried in the capacitor trench and the polysilicon of the transistor gate were deposited and formed at the same time.

It is okay to form them separately, and it is also okay to have different conductivity types. In this case, the gate insulating film and the capacitor insulator can be formed separately, and the gate insulating film can be a silicon thermal oxide film, and the capacitor insulating film can be a silicon nitride film or a multilayer film of silicon nitride and oxide. It can be of any type.

Further, in the present invention, polysilicon is another metal.

Alternatively, it may be replaced with an alloy such as silicide.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a schematic cross section of a conventional basic RAM cell. Further, FIG. 2 is a diagram showing the basic cross-sectional structure of a conventionally known memory cell in which a hole is drilled in a part of the conventional capacitor section in order to increase the effective area. FIGS. 3(a) and 3(b) are diagrams showing the first embodiment of the present invention, where (,) is a plan view thereof, and (b) is a sectional view thereof. Figure 4 (a), (b), (e), (d)
, (e), (f), and (g) are diagrams showing the manufacturing process and structure of the second embodiment, (a) to (f) are cross-sectional views, and (X) is a plan view. Further, FIGS. 5 to 7 are schematic diagrams showing the structures of the third to fifth embodiments, respectively. FIGS. 5 and 6 are plan views, and FIG. 7 (-) is a sectional view. (b) is a plan view. In the figure, 300 is a substrate, and 301 is a field insulating film. 302 is a channel stopper diffusion layer, 303 is an active part of a transistor, 304 is a gate insulator, 305 is an insulator for a capacitor, 306 is a drain contact part, 30
7 is a gate electrode, and 308 is a drain impurity layer. Further, 401 is a substrate, 402 and 403 are oxide films and nitride films for selective oxidation, 404 is a channel striker, 405 is a field oxide film, 406 is an impurity layer under the capacitor, 408 is a gate insulating film, and 409 is for the capacitor. The insulating film 2410 is an impurity implantation layer for transistor threshold control, 411 is a direct contact, 412 is polysilicon, 413 is a high concentration impurity layer under the direct contact, 414 is a gate electrode, and 415 is a source impurity layer. 7 more
01 is a silicon substrate, 710 is a channel stopper,
711 is a capacitor diffusion layer, 712 is an impurity diffusion layer in the source and drain portions, and 713 is an electrode on the capacitor. Pavilion 3 Zusai 4 Mouth

Claims (1)

[Claims] 1 switch, 1 switching MIS type field effect F transistor and 1
In a pair of charge temporary storage storage devices consisting of capacitors, an MIS field effect transistor is formed on the upper surface of a semiconductor single crystal that is formed at least partially into a pedestal shape, and a capacitor for storing charge is formed on the side surface of the pedestal. A charge temporary storage storage device comprising at least a portion of the charge storage device.