JPS607278A - Signal processor - Google Patents

Abstract

PURPOSE:To realize an emphasis circuit having the same emphasis amount as a conventional processor and having remarkably lower peak value of waveform than the conventional processor by providing a pre-shoot and an over-shoot to the waveform in using the emphasis circuit to a frequency modulation system. CONSTITUTION:The emphasis circuit Em is connected to an N-stage of shift register 1 to which a video signal is inputted and plural taps giving each time delay output provided to the shift register and consists on a coefficient device 2 giving weight coefficient series W1-WN symmetrically by taking an intermediate tap as the center so as to provide the emphasis characteristic and an adder 3 giving total sum of each output from the coefficient device 2. When a video signal as shown in Fig. (a) is inputted to an input terminal Sa of the circuit, a signal as shown in Fig. (b) is obtained from an output terminal Sb. Since the waveform shown in Fig. (b) has a waveform having pre-shoot and overshoot, a waveform having a peak value lower than broken lines S1 is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a signal processing device, and particularly to signal processing that performs emphasis and de-emphasis processing when recording and reproducing video signals on a recording medium such as a video tape recorder (VTR). Regarding equipment.

Conventional configuration and its problems Conventionally, in a VTR, for example, when a video signal is FM modulated and recorded and reproduced on a magnetic tape, it is necessary to reduce S/N deterioration of the reproduced video signal due to noise generated in the magnetic tape, etc. For this reason, a method is used in which the high frequency components of the video signal are amplified using an emphasis circuit and then recorded, and during playback, the high frequency components are reduced using an emphasis circuit to suppress the high frequency components of noise. However, since the band of the FM transmission line is limited by the electromagnetic conversion system, there is a limit to the increase in frequency deviation width due to the amount of emphasis, which limits the S/N ratio of the reproduced signal. was there.

OBJECTS OF THE INVENTION The present invention solves the above-mentioned conventional problems and
It is an object of the present invention to provide a signal processing device that can use a larger amount of emphasis than the conventional one with the same frequency deviation width as the conventional one in case of an M transmission line. Alternatively, the entire purpose of the present invention is to provide a signal processing device in which the peak value of a waveform is significantly lower than that of the prior art with the same amount of emphasis as the conventional one.

174th aspect of the invention The present invention has an emphasis circuit and a de-emphasis circuit, and the emphasis circuit has N stages (however, N stages).
a positive integer); and an adder circuit that weights and outputs the output signal of each tap of the tapped delay circuit (A'r-1 linear type 1-Lannuversal). The de-emphasis circuit has a transfer characteristic of 17.7cm or more, or has a characteristic substantially opposite to that of the emphasis circuit. A multiplication circuit that weights and outputs the output signals of the taps, and an adder that adds up the output signals of each of the multiplier circuits and outputs the results. be accomplished.

Description of examples Hereinafter, the present invention will be explained based on illustrated embodiments.

FIG. 1 is an example of a circuit using the present invention for applying emphasis to a video signal. This emphasis circuit Em
Q, an N-stage shift register 1 into which a video signal is input;
The weighting coefficients W1 to 1 are connected to a plurality of taps providing time-delayed outputs provided in the shift register, and are arranged symmetrically with respect to the intermediate taps so as to have an emphasis characteristic.
A coefficient unit 2 which provides W % f and an adder 3 which provides the sum of each output from the coefficient unit 2 are configured (14).

Figure 2 shows a de-emphasis circuit for reproduced signals using the present invention. It is a circuit. This de-emphasis circuit DEm is connected to the shift register 4 refined in the above stages (L≧N) and a plurality of taps provided in the shift register to provide respective time-delayed outputs, and has a de-emphasis characteristic. It is composed of a coefficient multiplier 5 which provides weighting coefficient sequences X1 to XL symmetrically with respect to the center of all the intermediate taps, and an adder 6 which provides a sum of the outputs of the coefficient multipliers 5.

The operation will be explained with reference to the waveform diagram in FIG.

The operation of the emphasis circuit will now be explained. Fourth
Figure 1 is a diagram of a conventional emphasis circuit 1o used in UVH3 type VTRs.

In Figure m4, the video signal applied to the input terminal 11 is output via the emphasis circuit 1o.

The emphasis circuit 10 includes a capacitor (capacitance value C1) 1
2. Resistance (resistance value Rb) 13. Resistance (resistance value Ra) 1
It consists of 4. Those values are, for example, CjXRb
= 1°3 μSeC, Rb + Ra = 5a.

When a video signal as shown in FIG. 3(a) is input to the input terminal 11 of the emphasis circuit 10, a signal as shown in FIG. 3(b) is obtained at the output terminal 16. In the case of a video tape recorder, the signal shown in Figure 3(b) is frequency-modulated and recorded on a magnetic tape. The signal is clipped at the points indicated by broken fa (sl) and broken line (S2) in Figure (b), and
The signal shown in C) is frequency modulated. Alternatively, by changing the constants of each part of the emphasis circuit 10 and, for example, setting the emphasis amount (=1±'') to +, the group 7 Blvi modulation is performed as a signal as shown in FIG. 3(d). .

In the case of 0 in FIG. 3, waveform distortion occurs, and the effect of D emphasis in FIG. 3(d) becomes +, causing a problem in that the S/N ratio of the pollution raw signal decreases.

Next, an example of the signal processing result according to the present invention will be explained with reference to FIG.

/j1 in Figure 6(a) to the input terminal Sa of the circuit in Figure 1
When such a video signal is input, a signal as shown in FIG. 6(b) is obtained at the output terminal sb. Figure 6 (b
The waveform shown in ) has a preshoot and an overshoot, so even though the amount of emphasis is the same as that in FIG. 3(b), a waveform whose peak value is lower than the broken line S1 is obtained. Next, when the video signal shown in FIG. 6(b) is input to the input terminal Sc of the de-emphasis circuit DEm shown in FIG. 2, the original signal shown in FIG. .

Here, it has been found that the shift register 4 of the de-emphasis circuit DEm shown in FIG. 2 needs to have N stages or more, and it is particularly desirable to have approximately 2N stages or more.

The reason for this is that when the number of stages of the shift register for the emphasis circuit is In, the number of stages is equal to 1, and for the de-emphasis circuit, it converges at 1. The number of stages of the emf 1 cis circuit Km is N, and the deenf 1 cis circuit DEm
Fig. 6 shows the results of calculating the deviation from the theoretical value of the frequency/signal level characteristics after emphasis and de-emphasis processing when the variables are set. If it is set to 2N stages, it falls within 1 dB, which is a characteristic suitable for practical use.

The video signal waveforms after the emphasis and tie-emphasis processing are shown in FIG. 6(C) and FIG. 6(d). Figure 5 (
c) is the result when the number of de-emphasis shift register stages is N stages, and FIG. 5(d) is the result when IrJ, 2N stages are used.

Looking at this result, the way the de-emphasis circuit comes out is N
It can be seen that although the signal is distorted in each stage, when all 2N stages are used, the original signal is sufficiently reproduced.

In the above description, it is assumed that a linear phase l'lance filter shift register is used, but the same effect can be obtained even if the entire circuit is made up of t analog elements and a delay line is used instead of the shift register.

Effects of the Invention As described above, when the emphasis circuit according to the present invention is used in a frequency modulation system, by giving the waveform a bristled overshoot, it has the same amount of emphasis as the conventional one, and It is possible to realize an emphasis circuit in which the peak value of the waveform is significantly lower than that of the conventional one, and to obtain the effect of significantly lowering the entire frequency deviation width than the conventional one without reducing the amount of emphasis. Alternatively, if the same frequency deviation width as before is used, it is possible to add more emphasis than before, and the S /
Nf can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an emphasis circuit according to the present invention,
Fig. 2 is a block diagram of an emphasis circuit that corresponds to the emphasis circuit of Fig. 1, Fig. 3 is a waveform diagram of processed signals by a conventional emphasis circuit, Fig. 4 is a block diagram of a conventional emphasis circuit, and Fig. 5 is Processed signal waveform diagram by the emphasis circuit and de-emphasis circuit according to the present invention, No. 6
The figure is a diagram of the signal level deviation tube 11 after emphasis and de-emphasis processing. Em: Emphasis circuit, 1: Shift register, 2: Coefficient unit giving emphasis characteristics, 3: Adder, DEm: Dimensions Emphasis circuit, 4...Shift register,
5...De-emphasis%I! Coefficient unit that gives +E, 6... adder. Name of agent: Toshio Nakao, 1 person Figure 4/θ Figure 5 Figure 6

Claims (1)

[Claims] It has an emphasis circuit and a de-emphasis circuit,
and a tapped delay circuit having N stages of the emphasis circuit u N stages (N positive integer), a multiplication circuit that weights and outputs an output signal of each tap of the tapped delay circuit, and each of the multiplication circuits. The adder circuit that adds and outputs the output signals of the circuit is constructed with a linear transversal filter (74), and the transfer characteristic to the de-emphasis circuit is approximately the same as that of the de-emphasis circuit. a delay circuit with taps having opposite characteristics and having N or more stages, a multiplication circuit that outputs the output signal of each tap of the tap E 1 circuit with a weight of 1, and the output signal of each of the multiplier circuits. 1. A signal processing device comprising a phase linear type 1-Lance Barsal filter equipped with an adder for adding and outputting.