JPS6084655A - Priority processing method for information transfer control - Google Patents

Abstract

PURPOSE:To eliminate the need to giving priority levels to all of input/output devices, and reduce the amount of circuit by setting only the number corresponding to a specific input/output device among plural input/output devices in a priority register. CONSTITUTION:A clock is normally supplied to the priority register 29, whose contents are updated. If a request for registering the number of the specific input device in a stack is made while the stack is full, the stack request is permitted only when a registration request having the number set in the priority register 29 or a higher priority number is made; and the permission of stack registration requests from other input/output devices are inhibited.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention transfers data between a plurality of input/output devices, accumulates all data from the input/output devices in a data buffer, and stores the main memory in a stack. Register a data transfer request to
In a bus conversion device that transfers data to and from the main memory according to the registration order of the stack, a priority register and comparison means are provided in the stack control unit that controls the stack, and data transfer requests for a specific range of input/output devices are processed. This is related to the priority processing method for information transfer control, which sets the all-priority register to give priority to registration when it cannot be registered in the stack.

[Prior art and problems]

FIG. 1 is a diagram showing the configuration of a data processing system. FIG. 2 is a diagram explaining the configuration of a data buffer, and FIG. 3 is a diagram showing the configuration of a bus conversion device. In the figure, 1 is a central processing unit, 2 is a main storage device, 3 is a channel device, 4-0 to 4-n are input/output devices, 5 is a first bus control unit, and 6
is a second bus control unit, 7 is a stack) 8 is a data buffer control unit, 9 is a data buffer, 10 is a selector,
Reference numeral 11 indicates a stack control unit, and BC indicates a conversion device.

In FIG. 1, all rows of data are transferred between the channel device 3 and the main storage device 2 using the first bus (..., and the data is transferred between the channel device 3 and a plurality of input/output devices 4-0 using the second bus). to 4-n. Channel device 3
The conversion device BC is connected to two buses and is a data converter that stores a fixed amount of data transferred from each input/output device 4-0 to 4-3 for each input/output device. ) Has a Kutsufa Buff.

For example, the first bus transfers data in units of 16 bits, and the second bus transfers data in units of 2 bits, for example. The time required for one data transfer is different.In accordance with this transfer unit, the data buffer is divided into two 16-byte nodes (data buffers A and B) for each input/output device, as shown in Figure 2. (i: Hold, used alternately.

Each input/output device 4-0 to 4-3 transfers data asynchronously with other input/output devices, and each has a different number "#0".
, "#1", ..., "#ru" are assigned.

The bus conversion device Be performs data transfer to each input/output device 4-0 to 4-n based on this number tone.

FIG. 3 shows the configuration of the bus conversion device BC. In FIG. 3, there is a stack 7 between the first bus control unit 5 and the second bus control unit 6, and the second bus control unit 6 determines that data transfer with the main storage device 2 is necessary. The number assigned to the input/output device is registered in the stack 7. The first bus control unit 5 transfers data between the data buffer 9 of the input/output device corresponding to the number output from the stack 7 and the main storage device 2 . When the data transfer is completed, the stack 7 is popped.

Conventionally, all second buses had input/output devices 4-0 or 4-.
If it becomes necessary to transfer data between the main storage device 2 and the main storage device 2 due to the data transfer performed with n, the data transfer using the first bus is automatically performed and the Priority processing is given to data transfer using the first bus only in this case. An example will be explained below.

Now, when the BOl of data buffer 9 is accessed from input/output device 4-0 of #0, buffer A and main storage device 2
An attempt is made to register a number in the stack 7 in order to perform data transfer with the . At this time, if the stack 7 can be registered, all its numbers are registered and data is transferred between the BO of one data buffer 9 and the input/output device 4-0. Thereafter, while the buffer 9 is being accessed, data transfer requests with the main storage device fi, 2 can be made. However, when the stack 7 is full and a new number cannot be registered, the number is not registered and the data buffer 90BO and input/output device 4-
Data is transferred to and from 0. Next, data buffer 9
When accessing B 1 k of , it tries to stack again. In such a control system, the stack control unit 1
The number of the input/output device that could be registered in the stack at 1 and 7 is set in a priority register (not shown). Next time another I/O device accesses the data buffer from the second bus, the number of that I/O device is compared with the contents of the priority register, and if the number of that I/O device is higher, the stack 7 Registration in the stack 7 is prohibited, and registration in the stack 7 is permitted when the values are smaller or equal. Here, when registration is prohibited, the number set in the 1 priority register is registered in the stack 7, and the contents of the priority register are rewritten to the number of the input/output device. When the number set in the priority register is registered in the stack 7 or when the stack 7 becomes empty, the priority register is reset and all input/output device numbers are prohibited from being registered in the stack 7. Priority processing is performed in this way, but this is effective for high-speed input/output devices, and when this method is adopted, the problem of one circuit being large is avoided. There is.

[Purpose of the invention]

The present invention is based on the above consideration (because there is a limit to the data transfer capacity of the bus, not only high-speed input/output devices are connected, but all input/output devices are In view of the fact that there is no need to prioritize, the overall purpose of this invention is to provide a priority processing method for information transfer control that reduces the amount of circuitry by limiting priority processing to specific input/output devices.

[Structure of the invention]

To this end, the priority processing method for information transfer control of the present invention provides a first bus used for data transfer to and from the main storage device and a second bus used for data transfer to and from a plurality of input/output devices. Data that is connected to the bus and sent to each of multiple input/output devices can be stored in fixed amounts.
Equipped with a buffer, a data buffer control unit, a first bus control unit, a second bus control unit, a stack for registering the number of an input/output device sent from the second bus control unit, and a stack control unit. , the second bus control unit transfers data to and from the plurality of input/output devices, accumulates all the data in the data buffer, and instructs the stack control unit to register all the numbers of the input/output devices; In a bus conversion device that transfers data to and from the main storage device according to the registered number by a first bus control unit, the stack control unit has a priority register and comparison means, and when the stack becomes full and There was a stack registration request for a number in the range of In this case, the number of the priority register and the number of the stack registration request are compared by the comparison means,
As a result, the above prohibition on permission of stack registration requests will be lifted on all conditions that the numbers are the same or the number for which the stack registration request was made is a higher priority number, and the above priority will be given depending on whether the stack is full or not. The present invention is characterized in that the priority register is reset on the condition that all registers are rewritten or reset, and the stack becomes empty.

[Embodiments of the invention]

Hereinafter, a non-inventive embodiment will be described with reference to all drawings.

FIG. 4 is a diagram showing the structure of one embodiment of the present invention.

In Figure 4, 21 to 24 are and goo), 2
5U Nando Gate, 26 and 27 are Or Gate, 28
is a comparator, and 29 is a priority register. Furthermore, among the input terminals of the logic gate, the terminal with a small circle displayed is an inverted input terminal. It is possible to set it in the priority register when it cannot be registered in the stack.

As an embodiment of the present invention, FIG. 4 shows a configuration in which 32 input/output devices are connected and input/output devices #0 to #3 are specified and prioritized.

In FIG. 4, the numbers of the 32 input/output devices are represented by signals NO to N4, with the NO signal being the most significant bit and the N4 signal being the least significant bit. Therefore, for a particular input/output device number #0 to #3, the signals of the turtle NO to N2 are all 60''.The signals of the NO to N2 are supplied to the inverting input terminal of the AND gate 21) N3 and N4. The signal is between one comparison input terminal A of the comparator 28 and the priority register 2.
9 bits P1 and P2 are supplied to the set input terminals.
The other comparison input terminal B of the comparator 28 is connected to the priority register 29
is connected to the set output terminals of bits P1 and P2 of. The priority register 29 consists of PPO, Pl, and P2.
Bit POvi - used as valid flag, PI)
and P2 are used as bits to store all input/output device numbers #0 to #3. The set input terminal of bit PO of priority register 29 is connected to the output terminal of AND gate 22, and the set output terminal of bit PO is connected to OR gate 26.
is connected to one inverting input terminal of the and gate 2
One input terminal of the AND gate 22 is connected to the output terminal of the AND gate 21 and one input terminal of the NAND gate 25, and the other input terminal of the AND gate 22 is supplied with a signal indicating that the stack is full. Ru. The other input terminal of NAND gate 25 is connected to the output terminal of comparator 28, and the output terminal of NAND gate 25 is connected to the other inverting input terminal of OR gate 26. The output terminal of OR gate 26 is connected to one input terminal of AND gate 24. The other input terminal of the AND gate 24 is supplied with a signal (stack registration request signal 1) outputted from the second bus control unit and indicating that a stack registration request is received. The output terminal of the AND gate 24 is connected to one input terminal of the OR gate 27 and sends a signal (stack registration request signal 2) indicating that there is a stack registration request to the stack control section. The other input terminal of the OR gate 27 is supplied with a signal from the stack control section indicating that the stack is empty. And Gate 2
A clock is supplied to one input terminal of 3, the output terminal of the OR gate 27 is connected to the other input terminal, and the output terminal of the AND gate 23 is connected to the set clock terminal of the priority register 29. . Note that the above circuit is
In the block diagram shown in FIG.
You can think of it as being in . Alternatively, a part of it may be considered to be in the second bus control section 6.

Next, the operation will be explained. First, to explain the normal state, since the priority register 290 bit Po is logic "0", it is not related to the output of the NAND gate 25 (, since the output of the OR gate 26 is logic rlJ, the stack registration request l As soon as becomes logic “1”, stack registration request 2 is issued.
is output to the stack control section. A clock is also supplied to the priority register 29, and the contents of the priority register 29 are updated.

Here, if the stack is not full, the stack control unit makes a signal tone "0" indicating that the stack is full, so the priority register 29 (P) PO remains at logic "0".

When the stack is full, the stack control unit sets the stack full signal to "1" and does not register to the stack. If the number of the input/output device is other than #0 to #3, the AND condition of the AND gate 21 is not satisfied, and the priority register 29 (P) PO is kept at logic "0". On the other hand, if there is a stack registration request with numbers #0 to #3, the AND condition of the AND gate 21 is satisfied, the pictograph PO of the priority register 29 is set to logic "1", and bits P1 and P2 are set to The number (#0 to #3) at that time is set. Next, consider the case where stack registration request 1 is input when priority register 290-bit PO is at logic "1".

If you receive a registration request for numbers other than #0 to #3,
The AND condition of the AND gate 21 is not satisfied, the output of the OR gate 26 is logic "0", and the stack registration request signal 2 is not output to the stack control section.

If a registration request with numbers #0 to #3 is received, the AND condition of the AND gate 21 is satisfied.

Here, the number registered in the priority register 29 and the current request number are compared by the comparator 28, and if the current request number is equal to or smaller than the registered number, then
Since the output of the gate 25 becomes a logic rule and the output of the OR gate 26 becomes logic "1", the stack registration request signal 2
is output to the stack control section. Also, priority register 29
The contents of the priority register are updated.

If the stack is not full, the stack control unit sets the stack full signal to "0", so the bit PO of the priority register 29 becomes "0". If the stack is full, the stack full signal is '1' and bit PO of priority register 29 is still '1', but
Bits P1 and P2 are rewritten to the same or smaller numbers as before.

Additionally, if data is transferred to and from the main memory without a stack registration request and the stack becomes empty, the stack empty signal from the stack control unit becomes logic "1". Therefore, a clock is supplied to the priority register 29, and the priority register 29 is reset.

As mentioned above, when a stack registration request is made for a specific input/output device number when the stack is full, the priority register is set, and from then on, the number set in the priority register or higher A stack registration request is permitted only when there is a registration request for a number with a high priority, and permission of a stack registration request is prohibited for other input/output device numbers.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, only the number corresponding to a specific input/output device out of a plurality of input/output devices can be set in the priority register, so it takes priority over all input/output devices. There is no need to rank them higher, and the amount of circuitry can be reduced.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the entire configuration of a data processing system, FIG. 2 is a diagram explaining the structure of a data buffer, FIG. 3 is a diagram showing the configuration of a bus converter, and FIG. 4 is an embodiment of the present invention. It is a diagram showing the configuration: 1... Central processing unit, 2... Main storage device, 3... Channel device, 4-0 to 4-rule.
...I/O device, 5...first bus control unit, 6...
2nd bus control unit, 7... stack, 8... data buffer control unit, 9... data buffer, 10.
... Selector, 11... Stack control unit, 21 to 24... AND gate, 25... NAND gate, 26 and 27... OR gate, 28... Comparator,
29...priority register, BC...bus conversion device. Patent applicant Fujitsu Limited (1 other person) Representative patent attorney
Kyotani 4 part 11 mouth

Claims (1)

[Claims] Connected to a first bus used for data transfer with the main storage device and a second bus used for data transfer between multiple input/output devices, and corresponding to each of the multiple input/output devices. A data buffer capable of storing a fixed amount of data sent as a data buffer, a data buffer control section, a first bus control section, a second bus control section, and an input signal sent from the second bus control section. The stack includes a stack for registering the number of the output device, and a stack control unit, and the second bus control unit transfers data to and from the plurality of input/output devices to accumulate data in the data buffer, and the stack In the bus conversion device that instructs a control unit to register a number of the input/output device, and performs all data transfer with the main storage device by the first bus control unit according to the registered number, the stack control unit: It has a priority register and comparison means, and if the stack is full and a stack registration request with a number in a specific range is rarely made, the number is set in the priority register as a condition, and the permission of stack registration requests is completely prohibited, and the above priority is set. If a stack registration request is made with a number set in the register, the comparison means compares the number of the priority register with the number where the stack registration request is rarely made;
As a result, the prohibition on permission of the stack registration request will be lifted on the condition that the numbers are the same or the number that received the stack registration request has a higher priority. A priority processing method for information transfer control, characterized in that the priority register is rewritten or reset, and the priority register is reset on the condition that the stack becomes empty.