JPS6093882A - Burst detection synchronization circuit - Google Patents

Abstract

PURPOSE:To increase the stability to temperature and secular change and also to decrease cost by digitizing most of the circuit, detecting a pattern specific to digitizing a burst signal and generating a synchronizing pulse. CONSTITUTION:An input signal 9 is inputted to a window comparator 10, a positive peak hold circuit 14 and a negative peak hold circuit 15. The output of the positive peak hold circuit 14 and the negative peak hold circuit 15 is inputted to a window comparator 10 to provide a reference voltage. The output of the window comparator 10 is inputted to a shift register 11, the output of the shift register 11 and a pattern generator 13 is inputted to a digital comparator 12, from which a synchronizing pulse 16 is outputted. Moreover, a burst is formed in the shift register 11 and a clock 17 whose phase is matched to the burst is inputted.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is directed to a burst detection synchronization circuit used to synchronize signals such as high-definition television (TV) that use burst signals as synchronization signals.・−・ It is related to.

Conventional configuration and problems thereof FIG. 1 shows a conventional burst detection synchronization circuit. The configuration of this conventional example will be explained below with reference to FIG. 1. In FIG. 1, 1 is a bandpass filter, and an input signal 7 is input to this bandpass filter 1. In FIG. Further, the output of the bandpass filter 1 is input to subtraction circuits 2 and 4. The output of the attenuation circuit 6 is input to the other input of the subtraction circuit 2.

The output of the subtraction circuit 2 is input to the delay circuit 3.
The output of is input to the other input of the subtraction circuit 4.

The output of the subtraction circuit 4 is input to a window comparator 5 and an attenuation circuit 6, and the window comparator 5 outputs a synchronization pulse 8.

Next, the operation of the above conventional example will be explained. In FIG. 1, a signal as shown in FIG. 2 is added as the input signal 7. This input signal 7 is a video signal to which a burst is added as a synchronization signal, and the polarity of the burst is inverted every time. Furthermore, the burst period is assumed to be time τ9, which corresponds to 1-3, . . .-in of the video. Assuming that the subtraction circuit 2 does not receive an input from the subtraction circuit 6, the input signal 7 is input to the switching delay circuit 3 after attenuating frequency components other than those near the burst frequency by the bandpass filter 1. . The subtraction circuit 4 calculates the difference between the input and output of the delay circuit 3, and the delay time of the delay circuit 3 is τ. so just]
The difference with the signal in front of the line is calculated. As is clear from Figure 2, the signal from one line before the burst has the opposite polarity, and the video signal has a strong correlation between lines and is almost the same signal, so in the end, the output of the subtraction circuit 4 is suppressed by the video signal. and burst only. Furthermore, the output is attenuated by a circuit 6.
By adding the signal to the subtraction circuit 2 through the signal, positive feedback is applied, and the degree of suppression of the video signal increases. The burst thus extracted has a waveform that rises slowly as shown in FIG. 3, and the polarity is reversed every time.

Since the output of the window comparator 5 is inverted when the absolute value of the input voltage exceeds a certain value, as shown in FIG. )) The timing is constant regardless of the polarity of ). Therefore, by using this output as the synchronization pulse 8 as a time reference, it is possible to synchronize the video. Also, it is possible to create a clock whose phase matches the extracted burst. However, in the above-mentioned conventional example, all of the blocks constituting the circuit are analog circuits, and there are problems in that level fluctuations, delay time fluctuations, etc. occur due to temperature changes and changes over time, and the timing of the synchronization pulse changes. Additionally, large and expensive components such as delay elements must be used, resulting in a high cost.

OBJECTS OF THE INVENTION The present invention eliminates the problems and drawbacks of the conventional example described above, and aims to provide a burst detection synchronization circuit that is stable against changes in temperature and over time at a low cost.

Structure of the Invention In order to achieve the above object, the present invention digitizes most of the circuit, detects a unique pattern when the burst signal is digitized with a gain of 5-, ---, and generates a synchronization pulse. By digitizing the circuit, temperature vs.
This has the effect of increasing stability over time and reducing costs.

DESCRIPTION OF EMBODIMENTS The configuration of an embodiment of the present invention will be described below with reference to the drawings.

In FIG. 5, 9 is an input signal, and this input signal 9 is input to the window comparator 10 and ((1) peak hold circuit 14 and ←) peak hold circuit 15. (1) The outputs of the peak hold circuit 14 and (→peak hold circuit 15) are inputted to provide a reference voltage to the window comparator 10.

The output of the window comparator 10 is sent to the shift register 11
The outputs of the shift register 11 and pattern generator 13 are input to the digital comparator 12,
A synchronization pulse 16 is output from the digital comparator 12. Further, a clock 17 that is generated from the burst and whose phase matches the burst is input to the shift register 11.

61 "2" Next, the operation of the above embodiment will be explained. In FIG. 5, a waveform like "2" in FIG. 2 is added as the input signal 9.

(1) Peak hold circuit 14 and (→ peak hold circuit 15.
The peak is held and the voltage is applied to the window comparator 10. The window comparator 10 obtains positive and negative threshold values as shown in FIG. 6(a) by dividing this peak voltage. This operation allows the threshold value of the window comparator 10 to be maintained at a constant level with respect to bursts even if the DC value of the video signal varies.

At that time, the output of the window comparator】O is shown in Figure 6 (b
). Furthermore, when this output is added to the serial input of the shift register 11 and a clock 17 with a phase as shown in FIG. 6(C) is added, the parallel output of the shift register 11 as shown in FIG. 6(C) is obtained. , ■ and O patterns are obtained.

This pattern is unique to bursts, so by comparing this pattern created in advance with the pattern generator 13 and the parallel output of the shift register 11 using the digital comparator 2, the matching signal can be detected. Synchronous pulse]6, the burst position can be detected. Although the probability of a video signal containing the same signal as a burst is low, it is not impossible, so protection can be applied using the periodicity of the synchronization pulse to prevent false synchronization.

In this embodiment, the number of analog circuit parts is small, and there is no need to use expensive and large components such as delay elements, so that it is stable with respect to temperature and can be made inexpensive.

Effects of the Invention The present invention has the above-described configuration, and provides the following effects.

(a) Since the analog circuit part consists of only a window comparator and a peak hold, it is stable against temperature and temporal fluctuations.

(b) Since large and expensive special parts such as delay elements are not used, the circuit can be made smaller and cheaper.

[Brief explanation of drawings]

Figure 1 is a professional diagram of a conventional burst detection synchronization circuit, Figure 2 is a waveform diagram of a composite video signal input to the burst detection synchronization circuit, and Figure 3 is a waveform diagram input to the window comparator in Figure 1. , FIG. 1 is an explanatory diagram of the operation of the window comparator, FIG. 5 is a block diagram of the burst detection synchronization circuit in an embodiment of the present invention, and FIGS. 6(a) to (C) are the same burst detection synchronization circuits. FIG. 9...Input signal, 10...Window comparator,
11... Shift register, 12... Digital comparator, 13... Pattern generator, 14...
(1) Peak hold circuit, 15... (→Peak hold circuit, 16... Synchronous pulse, 17... Clock. Name of agent: Patent attorney Toshio Nakao and 1 other person)
4 Figure 6

Claims (1)

[Claims] A window comparator that binarizes input signals including burst signals, a shift register that converts the time-series signals output from the window comparator into parallel signals, a pattern generator that generates parallel digital signals, and a parallel converter for the outputs of the shift registers. It consists of a digital comparator that compares the pattern with the parallel pattern output from the above pattern generator, and detects the match between the binarized pattern of the burst signal in the input signal and the pattern created by the above pattern generator, and synchronizes the input signal. A burst detection synchronization circuit characterized by taking the following characteristics.